This is a workaround for an issue with incremental compilation in the
SBT multi-project build that would require recompiling Chisel (and thus
everything) whenever any .scala file was modified.

RegFieldDesc: fix the output produced for undescribed registers

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Reduce Debug Module "flags"

Error: don't be an exception wrt. caching

Probably not a smart thing to build, but not illegal!

If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.

Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.

more detailed RegField descriptions

TLRegMapper: emit a JSON file describing the register fields

Add versions of the RegField functions to take it in, and
update Example device to use it.

Use bind from global namespace

Automatic PlusArg for emulator.cc

* Add another FPU hazard cover

* Add some PLIC covers

Teach MulDiv to do div-only

I also renamed badaddr to tval (the correct name).

MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.

therefore *everything* is now 1.0.4