- A BOOM core has its own TLB. Which needs a TL2 edge. And a PTW port.
   - Add edge implicit input to Core.
   - Widen CoreIO to accept a ptw_tlb port.
   - Modify RocketCoreParams to handle wider fetchWidths, retireWidths.
   - Hack PTW requestor count to accommodate extra PTW port.
   - Wire up PTW requestor to the core's TLB in the Tile.

becase reqs can be invalidated

It's redundant with the new scheme, so just adds HW for no reason.

We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.

Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554)

Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTi...

Update config override documentation

Fix up Absolute value.

As per https://github.com/ucb-bar/rocket-chip/pull/507

As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt.

Dev zero

We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.

* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts

Added access function

Added source accessor function in TLEdge

See https://github.com/riscv/riscv-isa-sim/issues/76

We were setting xPIE=0 instead.  This is a benign bug, but still a bug.

Dedup rocket

BankedL2Config: use the same LazyModule for all L2 banks

If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.