An incorrectly-set ready signal caused bad data to be read from the RAM.

@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.

* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock

ITIM

e99fa057 accidentally reversed them

DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.

It's a zero-width wire special case.

Closes #706.

This allows nicer-looking code to avoid generating lots of redundant nodes.

bump hardfloat

debug: Prevent writes to DATA/PROGBUF when busy

As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.

Add narrowData option to AsyncQueue.

Miscellaneous uncore cleanups