Dedup rocket

BankedL2Config: use the same LazyModule for all L2 banks

If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.

This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.

diplomacy: add :*= and :=* to support flexible # of edges

Most adapters should work on multiple ports.
This patch changes them all.

Rational clock crossing

This anticipates ucb-bar/chisel3#448. When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.

Physical optimization

coreplex: move TLBuffers for L2 and socBus

This lets smart caches exclude the sets that are filtered.

Cache cork