Support vectored stvec interrupts, too
https://github.com/riscv/riscv-isa-manual/commit/137812654e54e5d765e21909679a2a24a38be123
parent
c6135a02
Please register or sign in to comment
https://github.com/riscv/riscv-isa-manual/commit/137812654e54e5d765e21909679a2a24a38be123