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SimJTAG_remove_vpi

7f8d6f4d · Remove unnesessary VPI dependency from SimJTAG · Jun 11, 2018

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port-anno-rocket

10fa0b32 · changed the port anno so it uses a list of names instead of a mem mapping · Jun 04, 2018

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remove_pow2clockdivider_warning

af9f443e · Get rid of sim-only warning in Pow2ClockDivider · May 23, 2018

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pr-1443

37633bc7 · Guard against integer overflow on the DiplomaticSRAM size. · May 23, 2018

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dontdeleteme-singlestep

61c2e8c0 · Don't raise the single-step interrupt when in debug mode · May 14, 2018

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bump_riscv_tools

31ebda97 · Bump riscv-tools · May 01, 2018

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optional-ports

45e0e10d · tilelink: verbose fragmenter requires · Apr 24, 2018

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coherence-conf

ea21e261 · add support for multiple coherence protocols · Apr 06, 2018

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redo-1247

8845271e · rocket: appease lec? · Mar 07, 2018

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fcd

8c6e7456 · Bump chisel and firrtl (#1232) · Mar 01, 2018

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cs152-sp18-lab3

34796fe6 · riscv-tests benchmarks branch prediction counters · Mar 01, 2018

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february-core-pipeline-changes

0b41d931 · Fix mapping of acquire/release AMOs to fence operations · Feb 27, 2018

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rocket_covers

2e548c9a · Added functional covers · Feb 22, 2018

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publish-chisel-firrtl

7983ee26 · Change build to use local .ivy2 and publish Chisel and FIRRTL · Feb 21, 2018

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chisel2chisel3

a21dacbd · Fix up :Unit formatting. · Feb 02, 2018

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sbt-launch-update

a79a49e2 · move sbt-launch to match project/build.properties · Feb 01, 2018

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amazonf1

85abac87 · ResetCatchAndSync: work also in the context of a RawModule (#1202) · Jan 22, 2018

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cover_tag_ecc_error_during_fence_i

7c2df9f0 · Cover the case when there is an ECC error in DCache data array during fence.i execution · Dec 01, 2017

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boom-thesis-v2

ec13d939 · fix interrupt log · Nov 21, 2017

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try-invalidate

a74437e7 · Remove ras_update from FrontendIO · Nov 20, 2017

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