+ Remove parenthesized forms of asUInt();

mill: Bump to scala 2.13.10/chisel3.5.5

This follows cd49478d

Bump to scala 2.13.10/chisel3.5.5

feat: add github actions

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

feat: fix scala 2.13 removing Par

Scala 2.13 removed parallal collections from standard library in 2.13.
This commit adds the new repo as a separate dependency to fix that sbt
test can run successfully

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Bump scala to 2.13.8, chisel to 3.5.4

* Using snapshots can break downstream builds like in RC.
* There will be evictions and the hardfloat build can fail if new APIs
are used by Chisel in later snapshots

Co-authored-by: Michael Etzkorn <michael-etzkorn@sage.micro.com>

remove cloneType

Changing submodule protocol to https

Partially reverts f722163c

The reverted commit had the right idea but took a suboptimal approach.
Rather than one-hot-encoding the counter, we can reuse the divisor
register, thereby realizing the same circuit delay while eliminating
several flops.

Add AddRecFN and MulRecFN functional units

Ported from John Hauser's Verilog source
http://www.jhauser.us/arithmetic/HardFloat.html

Make DivSqrtRecFN_small tolerant to X-pessimism

In the recoded format, many bits are don't-cares for Inf, NaN, and zero.
Alas, taking advantage of that relies on sane processing of don't-cares,
which Verilog X does not have.

Luckily, in this case, the fix actually slightly reduces HW cost.

Revert bump.