Set the module name for many parameterized modules with chisel's desiredName

This code would actually cause an "high index XX is out of range" error

Support Mill 0.11

+ Remove parenthesized forms of asUInt();

mill: Bump to scala 2.13.10/chisel3.5.5

This follows cd49478d

Bump to scala 2.13.10/chisel3.5.5

feat: add github actions

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

feat: fix scala 2.13 removing Par

Scala 2.13 removed parallal collections from standard library in 2.13.
This commit adds the new repo as a separate dependency to fix that sbt
test can run successfully

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Bump scala to 2.13.8, chisel to 3.5.4

* Using snapshots can break downstream builds like in RC.
* There will be evictions and the hardfloat build can fail if new APIs
are used by Chisel in later snapshots

Co-authored-by: Michael Etzkorn <michael-etzkorn@sage.micro.com>

remove cloneType

Changing submodule protocol to https

Partially reverts f722163c

The reverted commit had the right idea but took a suboptimal approach.
Rather than one-hot-encoding the counter, we can reuse the divisor
register, thereby realizing the same circuit delay while eliminating
several flops.