We use unconditional jumps to reach these locations but I think the
RISC-V unconditional jump cannot express locations that are not aligned
to 4 bytes.

`riscv-rt`: Support for vectored mode interrupt handling

Add Mstatus helpers to allow setting fields in Mstatus

Also remove local bf_* helpers

Co-authored-by: rmsyn <117854522+rmsyn@users.noreply.github.com>

Allow `Mstatus` values to be directly written back to the CSR.

This adds a macro to generate `write(value:T)` function for writing a
structured value to a CSR.

And add a clarifying doc comment that this is an operation on Mstatus
values, not on the CSR itself.

Without needing to touch the CSR. This allows multiple changes in a
single register write.

`riscv`: register: fix target architecture conditional compilation

Uses `cfg(target_arch)` conditional compilation selectors for exported
macros, since `cfg` flags generated from `build.rs` are not present for
downstream users.

Implement Eq and PartialEq for Range and Permission

Tidy per-ext check-cfg flags

It's useful to be able to do equality tests for these for unit tests.

riscv: build: make `cfg` variables more robust

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Change which Cargo `CFG` environment variables are used to select the
custom `cfg` variables.

See
https://github.com/rust-embedded/riscv/pull/204#issuecomment-2094089195
for discussion.

`riscv`: register: exports macros for custom CSRs

Exports macros from the `riscv::register::macros` module for external users.

This allows external users to define custom CSR accessor functions.

This is useful for platforms and SoCs with custom CSR registers not
defined in the `riscv` crate.

Resolves: #187

Add Mstatus::from(usize)

Add some utility methods to Mstatus and Mcause

`riscv-rt`: make `abort` weak

This is useful unit tests that want test trap handlers.

Fix mistake in changelog