70: Add docs.rs document build metadata for build targets r=Disasm a=luojia65

This pull request changes build targets when build documents on `docs.rs`, it will show RISC-V targets other than default x86 targets.

Before:

![image](https://user-images.githubusercontent.com/40385009/116803431-2add2e00-ab4a-11eb-87ea-b1cd204299d2.png)

After (take `rustsbi` crate as example): 

![image](https://user-images.githubusercontent.com/40385009/116803427-2284f300-ab4a-11eb-8974-24126cbc4310.png

)



Co-authored-by: luojia65 <me@luojia.cc>

68: Bug fix for interrupt bit in `scause::set` r=Disasm a=luojia65

This pull request includes a bug fix. On RISC-V's cause register, first bit means is this cause an interrupt. The code before made a mistake to or an one bit when exception. After this fix, it correctly or an one bit when interrupt.

Related to https://github.com/luojia65/rustsbi/issues/10

. Thank you @wyfcyx

Co-authored-by: luojia65 <me@luojia.cc>

67: Fix register configuration and documents r=Disasm a=luojia65

This pull request contains:

1. Use `#[cfg(target_pointer_width = "32")]` other than `#[cfg(riscv32)]` to provide support on IDE lint and cargo doc outputs
2. Add `#[inline]` on most of `set` and `write` functions


Co-authored-by: luojia65 <me@luojia.cc>
Co-authored-by: Luo Jia <me@luojia.cc>

Co-authored-by: Vadim Kaushan <admin@disasm.info>

66: Fix link to RISC-V team in wg repo r=Disasm a=hasheddan

Fixes link to properly direct to heading in wg repo README.md.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>

Co-authored-by: hasheddan <georgedanielmangum@gmail.com>

Fixes link to properly direct to heading in wg repo README.md.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>

63: Fix unescaped "[]"s in doc comment r=Disasm a=longfangsong

When running `cargo doc` on this crate and crates depends on this crate, cargo will always raise `unresolved link` warnings for those `[h]` and `[x]`, which is annoying.

This pr escaped the `[` and `]` in these code to silence these warning.

Co-authored-by: longfangsong <longfangsong@icloud.com>

65: Small fixes according to RISC-V privileged specification r=Disasm a=luojia65

This patch contains following parts: 

1. RISC-V privileged specification v1.10 defined `TVM`, `TW` and `TSR` bits in `mstatus`, implement them in Rust.
2. Make `scause`, `stval`, `ucause` and `utval` writable. 
3. Add some comments for instructions when we need to update this crate into privileged version v1.12.

For part 2, these registers are defined read-write in specification, and are typically read in supervisor S-level. However in M-level there are some situations we should write values into them. This feature is used when M-level environment are transfering exception to S-level kernel.

Function `scause::set` contains somehow lots of code here, we need to write a `Trap` struct into it, but I don't know which way is the best to implement this function.

Co-authored-by: luojia65 <me@luojia.cc>

By @Disasm

57: Add mcounteren.rs, cycle[h].rs, instret[h].rs, and update mod.rs r=Disasm a=dkhayes117

I'm not sure the set_clear_csr!() macros are correct in mcounteren.rs.  I get a build error that says `cannot find function `_clear` in this scope`

Co-authored-by: dkhayes117 <dkhayes117@yahoo.com>

Update assert! logic in mcounteren.rs and scounteren.rs
Fix comment typo on `scounteren`

Add scounteren.rs
Implemented set_hpm and clear_hpm functions
Removed State enum, replaced with bool
Update comments to be more concise

Reformat mod.rs

Update hpm method to use an index from enum

Move mcounteren macros outside of Mcounteren type declaration

update mod.rs

53: Update link (riscv to risc-v) r=Disasm a=aDotInTheVoid



Co-authored-by: Nixon Enraght-Moony <nixon.emoony@gmail.com>

52: Add CSR register `medeleg`; small doc fix r=Disasm a=luojia65

mideleg is at 0x303; medeleg is at 0x302.

Co-authored-by: luojia65 <me@luojia.cc>

51: Fix {S,U}tvec::trap_mode() functions to match Mtvec::trap_mode() r=almindor a=Disasm

See also: https://github.com/rust-embedded/riscv/pull/50#issuecomment-647012575



Co-authored-by: Vadim Kaushan <admin@disasm.info>