Merge #65

65: Small fixes according to RISC-V privileged specification r=Disasm a=luojia65

This patch contains following parts: 

1. RISC-V privileged specification v1.10 defined `TVM`, `TW` and `TSR` bits in `mstatus`, implement them in Rust.
2. Make `scause`, `stval`, `ucause` and `utval` writable. 
3. Add some comments for instructions when we need to update this crate into privileged version v1.12.

For part 2, these registers are defined read-write in specification, and are typically read in supervisor S-level. However in M-level there are some situations we should write values into them. This feature is used when M-level environment are transfering exception to S-level kernel.

Function `scause::set` contains somehow lots of code here, we need to write a `Trap` struct into it, but I don't know which way is the best to implement this function.

Co-authored-by: luojia65 <me@luojia.cc>