[+] vhdl: interaction with zephyr via uart during RTL simulation was implemented. Module uart_sim was added. Found exception 'unaligned store' on function unlock_irq(key) (fixing in progress).

[+] msvc 64-bits target added and proper fixes for implicit conversion size_t to int.
[*] header file with license related to risc-v were modified.

[*] FPGA ROM hex-image files were updated. Zephyr is now default application (fwimage.hex).

[!] Bug fixes: UART sim status, Simulator event queue removing item
[+] Bootloader updated to support mepc register saving

[!] GPTimers added to makefile
[+] Scripting support to debugger's console improved (add wait(msec) and input via uart0 serial)

Check for failed invocations which would cause the debugger to crash.

Correct dependencies in various makefiles. Add -g flags globally to detect
crash causes. Force listen command to use correct IP address. Inform if no
appropriate IP is available.

[!] Swap (cooperative/preemtive) methods updated with intlock flag.

[!] GPTimer emulator memory map fix accordingly with HW

[+] FW sources and images updated to support irq_lock register in irqctrl.
[!] Fix in _Swap assembler method

[+] context switching added

[+] script support added.
[+] gptimers simulation model added

zephyr: remove unused drivers&files, initial risc-v build success. _Swap method not implemented (just stub)

zephyr: implementing linker.cmd script, fixing warning related to 64-bits platform. adding __start entry point that will be placed at 0x10000000 address

zephyr: gcc build initial version (linker error not fixed). elf64 support added for the offset generator

zephyr: added arch msvc and riscv64. Run nanokernel & shell example in msvc. cooperative and preemptive task/fibers switching tested

Adding Core's registers view command (regs) for simulation implementing access via DSU potentially compatible with HW

fix soc reset via debugger (stucked irq controller). DSU dummy registers address space was added to support future CPU run control debugging features and provide compatibility with simulation

linux fix: simulator multi-thread sync. System bus,greth classes were added. System events (Haps) implemented

doxy update (Ethernet setup, debugger help were added); fix in functional CPU model; thread exit fix

candidat v2 fix: bootrom bug fix that leads to corruption of SRAM entry point. Remove 2-dimen array on AXI data path that incorrectly synth. by Vivado