- Jul 31, 2017
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Palmer Dabbelt authored
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file. Signed-off-by:Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt authored
The RISC-V ISA defines a simple console that is availiable via SBI calls on all systems. This patch adds a driver for this console interface that can act as both a target for early printk and as the system console. Signed-off-by:Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt authored
This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems. Signed-off-by:Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt authored
This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt controller). Per-hart local interrupt controllers are found on all RISC-V systems. Signed-off-by:Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt authored
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the hardware from the clocksource driver by taking a pair of function pointers to issue the actual RISC-V specific instructions. Signed-off-by:Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt authored
Many ports (m32r, microblaze, mips, parisc, score, and sparc) use functionally identical copies of various GCC library routine files, which came up as we were submitting the RISC-V port (which also uses some of these). This patch adds a new copy of these library routine files, which are functionally identical to the various other copies. These are availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't used anywhere. Signed-off-by:
Palmer Dabbelt <palmer@dabbelt.com> Reviewed-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Palmer Dabbelt <palmer@dabbelt.com>
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Jonathan Neuschäfer authored
RISC-V needs a MAINTAINERS entry. Let's add one. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by:
Palmer Dabbelt <palmer@dabbelt.com>
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Stephen Rothwell authored
Signed-off-by:Stephen Rothwell <sfr@canb.auug.org.au>
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Stephen Rothwell authored
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Andrey Vostrikov authored
In support of a soon to be published MFD driver using serdev to talk to a supervisory processor that uses the CCITT-FALSE CRC16 variant in it's protocol, this patch was tested successfully on an i.MX6 ARM platform. Link: http://lkml.kernel.org/r/20170413142932.27287-1-andrew.smirnov@gmail.com Signed-off-by:
Andrey Vostrikov <andrey.vostrikov@cogentembedded.com> Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by:
Chris Healy <cphealy@gmail.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au>
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Pavel Tatashin authored
Early in boot Linux patches memset and memcpy to branch to platform optimized versions of these routines. The NG4 (Niagra 4) versions are currently used on all platforms starting from T4. Recently, there were M7 optimized routines added into UEK4 but not into mainline yet. So, even with M7 optimized routines NG4 are still going to be used on T4, T5, M5, and M6 processors. While investigating how to improve initialization time of dentry_hashtable which is 8G long on M6 ldom with 7T of main memory, I noticed that memset() does not reset all the memory in this array, after studying the code, I realized that NG4memset() branches use %icc register instead of %xcc to check compare, so if value of length is over 32-bit long, which is true for 8G array, these routines fail to work properly. The fix is to replace all %icc with %xcc in these routines. (Alternative is to use %ncc, but this is misleading, as the code already has sparcv9 only instructions, and cannot be compiled on 32-bit). This is important to fix this bug, because even older T4-4 can have 2T of memory, and there are large memory proportional data structures in kernel which can be larger than 4G in size. The failing of memset() is silent and corruption is hard to detect. Link: http://lkml.kernel.org/r/1488432825-92126-2-git-send-email-pasha.tatashin@oracle.com Signed-off-by:
Pavel Tatashin <pasha.tatashin@oracle.com> Reviewed-by:
Babu Moger <babu.moger@oracle.com> Cc: David Miller <davem@davemloft.net> Cc: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au>
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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