Fixes rems-project/sail#152

Fix crash when fcsr.frm is invalid

Fix incorrect SV48_Vaddr bitfield

tweak README for move to riscv organisation

Encourage use of `opam` and streamline by moving discussion of setting `SAIL_DIR` into a separate section about building using a custom Sail version.

Also tweak Makefile to remove new Coq generated files

This is required for implementing memory version support for CHERI.

It's possible that we might want to do page table walks at Privilege levels
other than the default value (e.g., under the explicit direction of the
instruction stream).  Split translateAddr into a thin wrapper of the same name
and a new translateAddr_priv that takes the Privilege as an argument.

Using the new riscv_mem functions to elide the Privilege level computation

- Expose "just below the periphery" functions that allow bypassing
  effectivePermission and instead take a Permission explicitly (as well as an
  AccessType, in the case of reads, to distinguish Read from Execute; for
  writes, just an ext_access_type that will be wrapped in Write).

Previously we were erroneously passing the instruction's memory access to lower
layers of the memory machinery.  For example, a store instruction still should
be attempting reads of PTEs, not stores.

This function was inconsistent in its use of arguments vs. globals.  However, in
all existing cases, the arguments are fed as the values of these globals, so
this has no observable impacts in the current model, but hopefully prevents
confusion later.

I have used this locally to build using a command like:

docker run -v $PWD:/sail-riscv -w /sail-riscv <docker-image> make csim

Thanks to @jameyhicks in #28 for showing how. Next step is to integrate this into github workflow somehow.

Fix the non-RVFI_DII build

Also run GitHub actions for PRs

This was broken by #76

macOS build fixes (with added fix for Ubuntu 18.04)

Add workaround for ubuntu 18.04 lack of pkg-config for libgmp.

Add support for the new RVFI_DII socket format

PMP address match misses some corner cases

Fix internal error caused by invalid LR / SC / AMO widths.

The RISC-V specification says:

"Software should not set the rl bit on an LR instruction unless the aq
bit is also set, nor should software set the aq bit on an SC
instruction unless the rl bit is also set. LR.rl and SC.aq
instructions are not guaranteed to provide any stronger ordering than
those with both bits clear, but may result in lower performance."

i.e. these instructions are allowed but do not have stronger atomicity
guarantees than the versions without the bits set. To implement this
we AND the rl bit on lr with the aq bit, and similarly AND the aq bit
on sc with the rl bit.

Prior to this patch these instructions would generate
Error_not_implemented in riscv_mem.sail . An alternative to this patch
would be to 'downgrade' the operations there but I think that would
risk future extensions calling mem_read / mem_write without being
made aware of these special cases (open to discussion).

Even though the relevant encodings are not currently valid it does no
harm to implement them in the obvious way.  It means it will be
trivial to enable them if they do become valid and extensions can
choose to implement them simply by adding the relevant decoding.

The RISC-V spec. only shows LR / SC / AMOs for word and double widths
even though the encoding would naturally extend to other widths (it is
a little unclear). Previously the Sail model would decode the unused
widths but throw an internal error in execute. With this change the
unused widths will not be decoded and will cause illegal instruction
exceptions instead.