Fix Error_not_implemented exception on lr.rl or sc.aq.

The RISC-V specification says:

"Software should not set the rl bit on an LR instruction unless the aq
bit is also set, nor should software set the aq bit on an SC
instruction unless the rl bit is also set. LR.rl and SC.aq
instructions are not guaranteed to provide any stronger ordering than
those with both bits clear, but may result in lower performance."

i.e. these instructions are allowed but do not have stronger atomicity
guarantees than the versions without the bits set. To implement this
we AND the rl bit on lr with the aq bit, and similarly AND the aq bit
on sc with the rl bit.

Prior to this patch these instructions would generate
Error_not_implemented in riscv_mem.sail . An alternative to this patch
would be to 'downgrade' the operations there but I think that would
risk future extensions calling mem_read / mem_write without being
made aware of these special cases (open to discussion).