It's an optional register.

Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.

OK'd by @palmer-dabbelt 

Cover all combinations of 32,64 bit XLEN with F and FD extensions.

Finishes Issue https://github.com/riscv/riscv-openocd/issues/110

I hope to use this in riscv-tools' regression.sh.

tests: bump env to pick up new names for CSRs

gdb gets target XLEN from register width now, so this is taken care of
automatically.

This makes it a little easier to just cut and paste from the log when
reproducing a failure. (The port number still needs changing though.)

Clean up VcsSim init()

Use a unique log file, so you can run multiple instances at once.
Add time out to waiting for the simulator to be ready.

* Probably implemented the changes required to support fadd test for rv32ud

* Created test files in rv32ud, implemented working(?) test for ldst

* fclass, fcvt_w, fmin and recoding seem to be working now

* Got fdiv (and sqrt) tests working

* fmadd tests seem to work

* fcmp works

* [WIP] fcvt working, but lacks a 32-bit implementation of the final test

* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST

* Added Makefrag for rv32ud tests and included in main isa Makefile

* Don't run 64-bit tests if the defined XLEN is 32

Closes #105.

Closes #103

Fixes --print-failures sometimes not actually printing out details about
failures.

debug: Fix the XLEN command line check

* Debug: Actually use the --32 and --64 command line arguments

* debug: make XLEN mismatch message clearer

misa is allowed to be hardwired to 0, so checking its U bit could
incorrectly suggest that U-mode is not supported.

When not passed, they are no longer printed out.

* debug: Need to apply remotetimeout before connecting to remote target

* debug: whitespace cleanup

Closes #89

This test would fail intermittently if gdb on the first hart managed to
set a breakpoint, resume, halt, and clear the breakpoint before the
second hart got a chance to resume.

Temporarily comment out MulticoreRegTest due to flakiness.

Follow-up to b68b3903.

The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.