* Before waiting for IPI by executing wfi instruction, MSIE bit
  should be set in mie CSR for other harts, else they will get
  stuck at the wfi instruction.

The time counter is enabled with the bit field set in `counteren` CSR.

add htif section in linker script, with ALIGNs to prevent MMIO and data from being placed on same page (#32)

Use IPIs to signal them.

* Support configuration for a 32-bit build.

* Regenerate configure.

We'll re-add support for the generic performance counter facility once
it exists.

It's vestigial; he didn't work on this project.