Signed-off-by: Zixian Cai <2891235+caizixian@users.noreply.github.com>

See: https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html

* Implement syscall readlinkat

* Implement syscall readv by read syscalls

Since pk lacks kernel-space dynamic memory management, we implement readv with
normal read syscalls rather than forwarding it to spike

It was originally added as a temporary hack to hide a race condition in
a prototype.  It should've been removed long ago.

Resolves #312

Signed-off-by: Zixian Cai <2891235+caizixian@users.noreply.github.com>

See: https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html

* Implement syscall readlinkat

* Implement syscall readv by read syscalls

Since pk lacks kernel-space dynamic memory management, we implement readv with
normal read syscalls rather than forwarding it to spike

It was originally added as a temporary hack to hide a race condition in
a prototype.  It should've been removed long ago.

Resolves #312

This reverts commit 54de960a.

See #298 for explanation.

There are many issues: 260, 285, 287 has to be solved

This workaround helps to add neccessary zicsr and
zifencei for cssr and fence.i accordingly.

Linux kernel simply return current brk when request brk addr is not
feasible. The pk should probably do the same.

This reverts commit 7ae86fb9.

This will continue to allow accesses to cycle/time via mcycle/mtime
despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297.
The hope is this will keep most people happy while doing the right thing
with Spike.

Regenerated the configure file using autoconf 2.71 to avoid the Syntax
error problem when running on OSX/AArch64.

Fixes #282

We previously kernel-panicked because that made it more obvious when a
syscall implementation was missing.  These days, it's more common that
the C library will do something sensible in response to returning -ENOSYS.
Favor that approach to avoid frustrating users.

The UART drivers all return -1 if no character is present, and so that's
what we should do if there's no UART at all.

See discussion on https://github.com/riscv-non-isa/riscv-sbi-doc/issues/82