Don't merge yet; it's still early days for this extension.

There's no such thing as "B", which continues to be a source of
confusion.  Time to fix that.

cc @ben-marshall since I added Zbkb/Zbkx.

Resolves #101

This commit roughly synchronizes privileged instruction table with the ISA
Manual with slight instruction order modifications, expecting instruction
tables in the ISA Manual are fully generated by riscv-opcodes,
not modified by hand.

This is based on:

*   riscv/riscv-isa-manual: commit f30a5f6de685
    ("Update chapters 2 and 7 for Hypervisor v0.6")
*   riscv/riscv-opcodes: commit 65af4131
    ("Virtual memory updates (#76)")

See https://github.com/riscv/riscv-v-spec/commit/c0275171f453bd0f2361b7dade47bddeb08fb7e5

h/t @a4lg

See https://github.com/riscv/riscv-isa-manual/issues/814

Instead of making (and depending on) multiple header files in external
repositories, this commit makes single intermediate file and copies it
to external directories on install.

This will...

*   Reduce CPU time (only slightly, though).
*   Enable making header file *without* cloning and destroying
    external repositories (`make encoding.out.h`).
*   Ensure that latest encoding.h is generated and copied on install,
    even after fresh checkout on an external source tree.

I forgot to add `senvcfg` in the previous PR.

* Add CSRs defined in Privileged spec 1.12 (non-H)

This commit defines additional CSRs defined in the privileged
specification, version 1.12 (diff is from 1.11) except...

-   Those defined in riscv-opcodes:
    -   mstatush
    -   mtinst
    -   mtval2
    -   mcontext
-   Those related to hypervisor extension

cf. <https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12>

* Add new CSRs defined in Privileged spec 1.12 (H)

New hypervisor-related CSRs, `henvcfg` and `henvcfgh` are added.
All other hypervisor-related CSRs are already implemented in
riscv-opcodes.

cf. <https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12>

This commit adds instructions defined in RISC-V Base Cache Management
Operation ISA Extensions, version 1.0.0-rc2 (now ratified).

https://github.com/riscv/riscv-CMOs

Update encoding.h to match recent Spike changes

Goal is to most closely match the hand-made changes to Spike's copy of
encoding.h, before we again start generating it from this repo.

This best matches Spike as of
https://github.com/riscv-software-src/riscv-isa-sim/commit/47aa83c2dda373bc266de2cb5fc85544cb7bdea8

Spike removed this in
https://github.com/riscv-software-src/riscv-isa-sim/commit/60243a3bf9f86de5b8b58807ae218f1e3aedc31c

I checked other uses of encoding.h (riscv-pk, riscv-test-env,
riscv-openocd), and confirmed that none of them use this value.

In Spike, I added these by hand in
https://github.com/riscv-software-src/riscv-isa-sim/commit/4730be82e63ec8bf4a30aa59afee5e5b58a0fbe4

Zbkx renames xperm.n and xperm.b as xperm4 and xperm8.

N has been deprecated in favor of bare S.

Removed SWAP16 opcode to avoid overlap with PKBT16

Add RISC-V P Extension v0.9.2 opcodes

scalar-crypto: post arch-review aes32* opcode change

- No instructions now share opcodes between RV32 and RV64.

- Removing extra logic from parse_opcodes which was added to handle this.

- Will also remove downstream logic in Spike to handle this too.

 On branch master
 Your branch is ahead of 'origin/master' by 1 commit.
   (use "git push" to publish your local commits)

 Changes to be committed:
	modified:   parse_opcodes

- After questions from the architecture review and subsequent cryptography
  task group meetings, we have stopped overlapping the aes32* and aes64*
  instruction encodings.

- We've done this in the name of removing complexity, because opcode space is
  not as tight as we thought it was when we originally overlapped them.

- Change affected by updating the aes32* opcodes only.

 On branch master
 Your branch is up-to-date with 'origin/master'.

 Changes to be committed:
	modified:   opcodes-rv32k
	modified:   parse_opcodes

* Add Svinval instructions
* Add PTE defines for Priv 1.12 and Svpbmt

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

The shamt field is 6 bits wide, so doesn't belong in opcodes-rv32i.

The opcodes-pseudo file still contains the RV32 versions with shamtw.