Commits · debug · github.com / riscv / riscv-opcodes

Mar 08, 2017
- Update the debug CSR definitions for the proposed 0.13 debug spec · 388bb93d
  Palmer Dabbelt authored Mar 07, 2017
  
  388bb93d
Dec 22, 2016
- Add Q extension · 3c1a9110
  Kito Cheng authored Dec 21, 2016
  
  3c1a9110
- Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space · 5f5c591e
  Kito Cheng authored Dec 21, 2016
  
  5f5c591e
Dec 07, 2016
- avoid non-standard predefined macros · 7650b391
  Andrew Waterman authored Dec 06, 2016
  
  7650b391
Aug 27, 2016
- Renumber misa; add performance counter CSRs · c86d2ee8
  Andrew Waterman authored Aug 26, 2016
  
  c86d2ee8
- Add mcontrol type constants. (#11) · 9f3e3894
  Tim Newsome authored Aug 26, 2016
  
  9f3e3894
Aug 26, 2016
- Re-rename trigger registers to be 1-based · 7d22c889
  Andrew Waterman authored Aug 25, 2016
  
  7d22c889
- Make hardware triggers match latest spec. · 1a25601e
  Tim Newsome authored Aug 25, 2016
  
  1a25601e
Jul 06, 2016
- Update to new PTE format · 16c63f38
  Andrew Waterman authored Jul 06, 2016
  
  16c63f38
Jul 01, 2016
- Remove instructions from privilege spec that are already in user spec · ea5ed10e
  Andrew Waterman authored Jun 30, 2016
  
  ea5ed10e
Jun 19, 2016
- Add README · 10b49ea8
  Andrew Waterman authored Jun 18, 2016
```
Closes #6
```
  10b49ea8
Jun 18, 2016
- Remove sasid (it's merged into sptbr now) · 6f4761cb
  Andrew Waterman authored Jun 17, 2016
  
  6f4761cb
Jun 10, 2016
- Update breakpoint spec · e9f43f8b
  Andrew Waterman authored Jun 09, 2016
  
  e9f43f8b
Jun 09, 2016
- Add breakpoint CSRs · 56696c7f
  Andrew Waterman authored Jun 08, 2016
  
  56696c7f
Jun 04, 2016
- Keep DCSR_XDEBUGVER unsigned. · 8a441f91
  Tim Newsome authored Jun 03, 2016
  
  8a441f91
Jun 02, 2016
- Update path to binutils · bc08d005
  Andrew Waterman authored Jun 01, 2016
  
  bc08d005
- Add dret instruction and debug CSRs. (#5) · 1783043a
  Tim Newsome authored Jun 01, 2016
  
  1783043a
May 14, 2016
- Remove arg lists from latex tables · c8bea5d3
  Andrew Waterman authored May 13, 2016
  
  c8bea5d3
- Rename "Device Interrupt" to "External Interrupt" · e9eb2c4e
  Andrew Waterman authored May 13, 2016
  
  e9eb2c4e
May 03, 2016
- Remove mipi registers · 0f222ecd
  Andrew Waterman authored May 02, 2016
```
IPI pending registers will live outside the core, so they can cause wakeup.
```
  0f222ecd
- Remove tohost/fromhost · 4741340c
  Andrew Waterman authored May 02, 2016
  
  4741340c
May 01, 2016
- Remove mcfgaddr; change memory map · af5e124a
  Andrew Waterman authored Apr 30, 2016
  
  af5e124a
- Remove mtimecmp · 2baef21d
  Andrew Waterman authored Apr 30, 2016
  
  2baef21d
- ERET -> xRET · 86c755bb
  Andrew Waterman authored Apr 30, 2016
  
  86c755bb
Apr 07, 2016
- Remove nonstandard stats, uarch CSRs · 60f3a8e3
  Andrew Waterman authored Apr 06, 2016
  
  60f3a8e3
Mar 10, 2016
- Allow immediates for write_csr; check for signedness · fee20f1c
  Andrew Waterman authored Mar 10, 2016
  
  fee20f1c
- Reflect new location of encoding.h in riscv-pk · b4125c05
  Andrew Waterman authored Mar 10, 2016
  
  b4125c05
Mar 04, 2016
- Update CSR encoding · 080ec44b
  Andrew Waterman authored Mar 03, 2016
  
  080ec44b
Feb 29, 2016
- WIP on priv spec v1.9 · 53d732e4
  Andrew Waterman authored Feb 28, 2016
  
  53d732e4
- WIP on priv spec v1.9 · 9b7dce61
  Andrew Waterman authored Feb 28, 2016
  
  9b7dce61
Feb 06, 2016
- WIP on priv spec v1.9 · baed8813
  Andrew Waterman authored Feb 05, 2016
  
  baed8813
Jan 14, 2016
- remove hwachaV3 definitions · cd97d2f4
  Colin Schmidt authored Jan 13, 2016
  
  cd97d2f4
Nov 13, 2015
- add miobase, mipi; drop send_ipi · b29f84fd
  Andrew Waterman authored Nov 12, 2015
  
  b29f84fd
Nov 06, 2015
- Revert "Revert "Enable the four custom instructions"" · 291c3548
  Andrew Waterman authored Nov 06, 2015
```
This reverts commit fe574261.
```
  291c3548
Oct 21, 2015
- Update to hopefully final RVC 1.9 encoding · bdcf0eb0
  Andrew Waterman authored Oct 20, 2015
  
  bdcf0eb0
Oct 13, 2015
- rvc 1.8 candidate · f308f969
  Andrew Waterman authored Oct 12, 2015
  
  f308f969
Oct 06, 2015
- move towards RVC 1.8 · f4333ac5
  Andrew Waterman authored Oct 05, 2015
  
  f4333ac5
Sep 29, 2015
- In C headers, keep instructions in original input order · 76f508c8
  Andrew Waterman authored Sep 28, 2015
  
  76f508c8
- Include pseudo-ops in inst.chisel · 2669f5ed
  Andrew Waterman authored Sep 28, 2015
  
  2669f5ed
Sep 09, 2015
- No need to provide GCC with encoding.h anymore · 369da995
  Andrew Waterman authored Sep 08, 2015
  
  369da995