This greatly reduces the amount of spinning in the debug loop spike does
when DEBUG_ROM_FLAGS are written by the debug module, because now it's
not getting a cached version over and over again.

Test using riscv-tests/debug. Debugging still works.

Fixes build.

Previously gcc would complain that link.lds was mentioned twice (once on
the command line and once with a -T directive.)

Update for counter related CSR 

Normally, csrs will reuse the checks in verify_permissions of its base csr type
This modification will not cause any functional change, just reuse the check
in csr_t class to check whether it writes to read-only csr instead of checking
writes to counter_proxy_csr_t by itself.

Hopefully for the last time :-)

add support for m/henvcfgh and mconfigptr CSRs 

Fix misaligned HLV/HLVX/HSV

It was accessing memory using the current privilege mode instead of
the expected guest privilege.

Once #872 is fixed, I suspect we can greatly simplify this.

They were accessing memory using the current privilege mode instead of
the expected guest privilege.

Once #872 is fixed, I suspect we can greatly simplify this.

It was previously necessary because we were shifting left before
assigning to a reg_t, but that changed in the previous commit.

prv can never be larger than PRV_M

- If U-mode is not supported, then registers menvcfg and menvcfgh do not exist
- Since H extension requires S-mode, and S mode can not exsit without U-mode,
so senvcfg, henvcfg/henvcfgh also do not exist if U-mode is not supported

- MPRV is read-only 0 if U-mode is not supported
- If U-mode is not supported, UBE is read-only 0
- If S-mode is not supported, SBE is read-only 0

the default target endian is always little endian:
- mmu::is_target_big_endian() return false
- sim_t::get_target_endianness() return memif_endianness_little
when RISCV_ENABLE_DUAL_ENDIAN  macro is undefined

separate function compute_mstatus_initial_value()

Since the last step is about to get much more complex

Since the middle step is about to get much more complex

Conditionalize Smepmp extension (ePMP) support

Fix #1044

These have never been logged properly.

Otherwise they will have the same problem as #1044

Use this for mstatus on RV32 so that `csrw mstatus` does not modify
the bits in `mstatush`. Fixes #1044.

Mask in underlying CSR is sufficient.

Mask field in rv32_high_csr_t is now unneeded and will be removed next.

The mseccfg only exists when enabling the Smepmp extension. If not
enabling the Smepmp extension, CSR instructions to the mseccfg raise
illegal instruction faults, and the PMP behaviors as hardwiring mseccfg
0 (the reset value of mseccfg).

Add support for smstateen 1.0.0

The privileged spec allows writes to pmp(i-1)cfg with locked pmp(i)cfg
(According to a recent discussion: https://github.com/riscv/riscv-isa-manual/issues/866)