Make it clear that on reset, the triggers are also reset. The defined
values already ensure that triggers are disabled when they have their
reset values.

Last change for #913.

Trigger CSRs provide access to underlying triggers.

In response to #913.

Refer to "trigger registers" as "Trigger Module Registers"

Issue raised in #913.

uncertain is updated when trigger fires.

Don't make this contingent on hit0/hit1 being changed, since those bits
are optional. (Although I discourage anyone from not implementing
hit0/hit1.)

Addresses #915.

Make register dump output more concise.

Add `show` argument that lets user decide how to deal with fields whose
value is 0:
* Show them all.
* Show them if they have a symbolic name.
* Don't show them.

Use underscores instead of whitespace in field names, so we don't need a
comma in the separator.

New format:
```
{datacount=2 cmderr=not_supported}
{version=0.13 anyresumeack=1 allresumeack=1 impebreak=1 authenticated=true anyhalted=1 allhalted=1}
```

The last field of a register was not printed

Fix macro generation

1) We need to add ULL modifier to all values to fix some issues with `set_field` and `get_field` OpenOCD macros (for example, when `mask` = 1 << 31, it leads to UB becuase of signed overflow)

`riscv_debug_reg_fields_to_s()` exited early without processing the last
field.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>

AR: Comment itrigger limited to 32 ints if XLEN=32

AR: Comment etrigger limited to 32 exceptions if XLEN=32

Resolves #904.

Addresses #905, which reports that in 1.13 higher exception codes will
be used.

AR: Clarify itrigger and trigger number translation

itrigger numbers relate to the value written to *cause when the trap is
taken.

Addresses #889.

AR: Clarify itrigger behavior.

Specifically, make clear that itrigger fires *after* the original
exception has finished updating all the CSRs.

Hopefully resolves #890.

Add people with git PRs to credits.

AR: Update priority table from latest privspec

Add everyone who had a PR merged that changed the spec itself.

Addresses #892.

AR: Clarify triggers and multiple state changes

Incorporate more feedback from AR. Moved this into a separate Sdtrig
section, since the discussion could also apply to instructions that
cause triggers beside memory access ones. (E.g. an instruction that
combines memory accesses with a trigger, and itrigger.)

Follow up to #883.

Accidentally pushed to master instead of a feature branch.

This reverts commit 79e33fb7.

Incorporate more feedback from AR. Moved this into a separate Sdtrig
section, since the discussion could also apply to instructions that
cause triggers beside memory access ones. (E.g. an instruction that
combines memory accesses with a trigger, and itrigger.)

Follow up to #883.

mcontrol: Behavior is undefined because it's deprecated.

mcontrol6: If a trigger reports hit=before then some memory accesses may
have been performed. If it reports immediately after, then all accesses
have already been performed.

* AR: Clarify what tmexttrigger.intctl is for

Addresses #891.

* Add missing article

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

---------

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

AR: Clarify why icount matches on every trap.

AR: Clarify section/chapter in Sdext.

Addresses #894

Clean up Makefile a little

AR: tcontrol.mie applies to all traps, not just breakpoints

AR: Remove Message Registers.