Previously they were emitted in Chisel._ (compatability mode). As part of upgrading to chisel3, export them as chisel3 (note this doesn't actually change anything).

* Document forward progress guarantees in Debug Mode.

Alternative to #481.

* Small progbuf execution clarifications.

* Rewrite/clarify DM Reset Control

Hopefully fixes #480.

* Clarifications from review.

* Another clarification.

* There's no way to tell when reset has started.

I don't think that's very important. If it is, we'll probably have to
add a status bit that indicates a hart is held in reset.

* Fix wrong table reference

The label is named dtmTable:jtagregisters, not table:jtag_registers.

* Remove reference to non-existent table

The referenced table was removed in
b0420b3a.

Alternative to #488.

Addresses #489.

The spec says about the dmcontrol.hartreset field:
 "If this feature is not implemented, the bit always
stays 0, so after writing 1 the debugger can read
the register back to see if the feature is supported."

That makes it a WARL field not a R/W field. Changing the annotation to
make it more obvious to the reader.

Email addresses are typically given like "<email@example.com>" with no
spaces. That was the case for Tim's email address, but not for the other
one. Fix that for consistency (it's the title page after all!)

These were showing up as ??? in the output document.

* Update implementations.tex

In the suggested implementation which uses memory map, clarify that the region should only be accessible in Debug Mode.

If this region is accessible in non-debug Mode, it is unclear how the Debug MOdule is supposed to interpret the interactions with the memory regions specified here.

* Update implementations.tex

core -> hart for consistency

* Update implementations.tex

Pluralize "harts" as several harts may be in debug mode at once.

* Update registers.py to use Python 3

Python 2 is on its way out, switch the script to Python 3 instead.

* Update Travis to use Python 3

* Tighten up trigger specification.

This contains a bunch of improvements that came out of an e-mail
discussion. The biggest one is that it specifies the priority of various
triggers compared to the exceptions already in the Privileged Spec.

* dmcontrol->mcontrol, fix cut and paste mistakes.

* All trigger fields are WARL.

It already said this in Trigger Registers: "All {\tt tdata} registers
follow write-any-read-legal semantics."

* supported->legal

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Incorporate minor feedbacks.

* Trigger PC is set to next instruction to execute.

Previously on precise timing=after exceptions we said it should be set
to the PC of the matching instruction. But that doesn't work well
because the debugger can't know if triggers are precise or not.

* Tweak trigger priorities.

Add itrigger/etrigger.
Move mcontrol after (on previous instruction) to top priority.

* Fix typo.

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Clarify mcontrol load before side effect.

* Clarify trigger priority table.

It really should be in the S-mode section of CSRs, but that would be an
incompatible change. Fixes #410.

This change might break debuggers that are written to support 0.13.
OpenOCD and Lauterbach have stated they're fine with that, and there
probably aren't that many other debuggers out there. The fix will be
trivial.

* Numerous tweaks, responding to Marc Gauthier

See https://lists.riscv.org/g/tech-debug/message/755



* Rename W to WARZ.

* W1 fields should read 0.

* Rephrase hartinfo.dataaccess.

* Abstract reg access may fail depending on state.

* Register increment may not happen when transfer=0.

* Clarify writing command while busy=1.

* may is ambiguous, might is unambigous

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Rephrase behavior when writing command while busy.

* Update same sentence everywhere.

* Addressing more feedback from Marc Gauthier.

See https://lists.riscv.org/g/tech-debug/message/756



* Clarify that stepie affects NMI as well.

* exception->trap

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* exception->trap

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* exception->trap

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* exception->trap

Co-Authored-By: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Most fiels in mcontrol are WARL.

Fixes #410.

* Clarify mcontrol.size.

My attempt to fix #455.

* Fix cut and paste error.

* Fully qualify register/field macro names.

This solves the problem we have with the same field existing in multiple
registers, as reported in #451.

* Turns out we do need serial.tex.

It's used in riscv-debug-workgroup-notes.pdf which is built by default.

* Fix \F and \R in serial

Defined ebreaks and ebreaku as WARL fields that are 0 if the associated mode
is not supported by the hart.

Fixes #454.

access.

Recommend that we attempt to match every address that is accessed.

See #436. Does this change need to go in 0.13 as well?

Fixes #438.

This bug was reported (with a fix) way back in 2003 (7 years before
RISC-V was started at Berkeley) at
https://www.latex-project.org/cgi-bin/ltxbugs2html.new?pr=tools/3512

For us, it should fix #432. I'll apply this to the release branch once
it merges to master.