Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

maskmax=0 means match=1 is not supported.
There must be at least one 0 bit in the tdata2 when using match=1.

Addresses #586.

Addresses part of #565.

* Add version 1.0 value to dtmcs.version field

* Use dtmcs.version value 1 for both 0.13 and 1.0

Excluding clarifications, which don't change the spec.

* Add clic bit to tmexttrigger.

Addresses #412.

* Don't limit to CLIC.

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* clic -> intctl

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Explain how to simply write any trigger.

Addresses #573.

This new requirement only changes hardware with writable types. Even
there it is trivial to implement as long as types 2 or 6 are supported,
and those types become selected when 0 is written.

* Fix typo.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Clarify trigger CSR behavior when XLEN changes.

Addresses #583.

* 32-bit writes clear inaccessible bits.

* Writes to *registers* clear inaccessible bits.

* add dmstatus.ndmresetpending

* add dmstatus.ndmresetpending

* Apply suggestions from code review

Co-authored-by: Tim Newsome <tim@sifive.com>

* Apply suggestions from code review

Co-authored-by: Benjamin Staveley <bstaveley@ventanamicro.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

Addresses #572.

* AMO operations may be ignored by mcontrol triggers.

Also some formatting cleanup to make things more consistent.

* Addresses are available but data might not be.

* Also update mcontrol.

* Add keepalive feature.

This allows a debugger to request that a given hart stays available for
debugging (e.g. is not powered down). Fixes #519.

* Remove keepalive status reading.

* writes -> sets

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Make the example more conservative.

Feedback from Robert Chyla.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Added sbytemask field to textra32 and textra64

sbytemask field in textra32 and textra64 provides byte-granular comparison of the svalue trigger value to the scontext CSR

* Update xml/hwbp_registers.xml

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Added comments about sbytemask

Byte masking of svalue comparison only applies when sselect==1.

* Update hwbp_registers.xml

* Update hwbp_registers.xml

* Update hwbp_registers.xml

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

This helps some hardware implementations be simpler.  Addresses #550.

We used to not do this because those fields would often have the same
name as some other field, and there was a name collision. Now however we
have long, fully qualified names. This change is needed for #588 which
references \FcsrTextraSixtyfourSselect.

Fixes #462.

* Recommend mprven=1

* Review feedback: links

* Add pending state/bit to icount.

See mailing list. Subject:"On icount triggers"

* Fix typo.

* Explicitly mention s/u bits are 0 if not supported.

* Allow count decrement when triggers are disabled.

This reverts #557 because the issue raised in #555 is already solved by
the new pending bit.

Fixes #448

* textra32/64 also affects the new mcontrol6 triggers

* Provide clarity on textra64.  Don't refer to non-existent textra.

* List all DM registers in Table 3.8.

But don't give them each a description if it's redundant.

The main change here is that registers.py now generates an "index" table
that can be split across pages.

This change supersedes #560.

* Review feedback.

* Add support for the A extension

* Review feedback

* Handle instruction mnemonics consistently.  Reduce empty space.

* Remove all uses of the ambiguous term "may not"

* Review feedback

* It's legal to implement the CSRs even if there are no triggers

Co-authored-by: Tim Newsome <tim@sifive.com>

heterogeneous systems with some control processor harts that only support M
mode and some full-featured harts that support more.

* Added exttrigger capability as type 7

* Review feedback.
- don't limit implementation to a pulse
- allow multiple inputs to be selected and fire if any of them signals

* Revert PDF

* Change names to DM external trigger and TM external trigger

* Define TM

* Debuggers should know when harts are unavailable.

Make unavail sticky, needing to be acknowledged with new ackunavail bit.

This is a backwards incompatible change. I think it's OK because
implementations that support unavailable harts are rare (I don't know of
any), and the change only means that debuggers must be updated. If
hardware doesn't implement this then everything will still work,
although users might not be notified when harts become unavailable.

Fixes #461.

* Add stickyunavail bit.

Every other way to ensure hardware backwards compatibility was getting
too convoluted.

* Clean up a little.

Keep definition of the bits in the register definition, and definition
of states in the DM section.

* Don't decrement icount.count when exception is blocked by tcontrol.mte

Since it wouldn't be able to take the breakpoint trap anyway.

Fixes #555.

* Expand count decrement exception to include other trap-suppression mechanisms

Thank you!

Co-authored-by: Benjamin Staveley <ben@Benjamins-MacBook-Pro.local>

* clarify that PMP must allow access for debug to be possible

* rephrase

* Update implementations.tex

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Add most hypervisor support

* Don't check in PDF changes.

* Add vu/vs bits to various triggers
Clarify that registers are "accessible" in specified modes, not just "writable"
Prohibit hcontext alias when the H extension isn't supported since this is in
  the CSR address space that's normally just for hypervisor.

* Clarify that the backwards-compatible mscontext is optional.

* Update core_debug.tex

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Fix curly braces

* Fix textra64.mhselect
Remove comments about future H mode support

* scontext is accessible from VS mode.
Clarify in various places that enables are for "S/HS" instead of just "S" mode.

* Use decimal values in field descriptions to match the rest of the spec.
VMID is in hgatp, not satp.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>