Issue #180

Fixes Issue #176

Fixes Issue #175.

* Add explanation about how \Fndmreset and actual system reset are related.
Also clarify that havereset bits are not affected by dmactive

* reset: be more explicit about available status

* reset: use legal macros

* debug: fix macros

* debug: of vs to

* reset: unavailable vs unavail

* havereset: unspecified behavior when dmactive low

Refer to ISA and priv docs.

* Explain cache coherency wrt to system bus access

I suspect we'll have to do something for systems that don't implement
the Program Buffer, but let's get this ball rolling at least.

Issue #140

* fences aren't guaranteed to affect caches.

* Make description more abstract.

Only refer to caches in a parenthetical.

Issue #115

Add an index to the document.

Also turn all register fields into hyperlinks to their definition.
Hopefully this is enough to satisfy #142.

* DM: Add hasreset and hasreset ack bits to DM Registers. Move other newly added fields to more aligned locations.

* Debug Module: Add explanation for hasreset

* hasreset clarifications

* More clarifications for hasreset

* hasreset typo (cleared 'by')

* hasreset: Move dmerr and put impebreak back where it was

* hasreset: more clarifications

* HasReset : Renamed to "Have Reset"

* havereset: unnecessary 'the'

* Update debug_module.tex

* spaces not tabs

* space not tabs

* havereset: Rename the ack bit to be more clear that it is acking the havereset, not that it has some quality

* hasreset: Update PDF

haltreq, resumereq, hartreset are per-hart bits

Include pdf.

Fixes #166.

Add \Fimpebreak, to support of implicit ebreak.

Add legend to the  Abstract Command State Machine Diagram

Remove reference to 'H' mode from the figure

Remove hmode reference, to fix build.

Issue #160.