The table still *just* fits on the page.

Issue #198

This reverts commit e698a500.

The table still *just* fits on the page.

Issue #198

Clarify that we deal in physical addresses only.

Issue #110.

Clarify that \Fdatasize contains at most 12.

This reverts commit f7da066d.

Issue #110.

Issue #193.

Use a different word than "clobbered"

Add missing "to"s to abstractauto description

Correct plurality of halted harts in haltsum

Since more than one hart can be halted at a  time, correct this statement.

Put parens around all macros that need it.

This reverts commit 26d76a00.

This was supposed to be on a separate branch so there could be a PR.

This allows a single-core system to wire all these bits to 0, and lets
eg. a 4-core system only use 2 bits instead of 10.

I had thought this is the way it was, but clearly not.

Since this is a backwards incompatible change, I'm incrementing the
version number.

Correct compressed version of ebreak

Clarify some single step corner cases.

Issue #121. There's too much emphasis on what not in this change, but
I'm not sure how to rephrase it to be positive.

Fixes Issue #176

Fixes Issue #175.

* Add explanation about how \Fndmreset and actual system reset are related.
Also clarify that havereset bits are not affected by dmactive

* reset: be more explicit about available status

* reset: use legal macros

* debug: fix macros

* debug: of vs to

* reset: unavailable vs unavail

* havereset: unspecified behavior when dmactive low

Refer to ISA and priv docs.

* Explain cache coherency wrt to system bus access

I suspect we'll have to do something for systems that don't implement
the Program Buffer, but let's get this ball rolling at least.

Issue #140

* fences aren't guaranteed to affect caches.

* Make description more abstract.

Only refer to caches in a parenthetical.

Issue #115

Add an index to the document.