- Jan 04, 2018
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Megan Wachs authored
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- Dec 23, 2017
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Tim Newsome authored
Put parens around all macros that need it.
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Tim Newsome authored
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- Dec 19, 2017
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Tim Newsome authored
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Tim Newsome authored
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Tim Newsome authored
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- Dec 16, 2017
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Tim Newsome authored
This reverts commit 26d76a00. This was supposed to be on a separate branch so there could be a PR.
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Tim Newsome authored
This allows a single-core system to wire all these bits to 0, and lets eg. a 4-core system only use 2 bits instead of 10. I had thought this is the way it was, but clearly not. Since this is a backwards incompatible change, I'm incrementing the version number.
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- Nov 28, 2017
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Megan Wachs authored
Correct compressed version of ebreak
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mwachs5 authored
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Megan Wachs authored
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Megan Wachs authored
Clarify some single step corner cases.
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Megan Wachs authored
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- Nov 23, 2017
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Tim Newsome authored
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Tim Newsome authored
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- Nov 22, 2017
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Tim Newsome authored
Issue #121. There's too much emphasis on what not in this change, but I'm not sure how to rephrase it to be positive.
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Tim Newsome authored
Fixes Issue #176
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Tim Newsome authored
Fixes Issue #175.
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- Nov 18, 2017
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Megan Wachs authored
* Add explanation about how \Fndmreset and actual system reset are related. Also clarify that havereset bits are not affected by dmactive * reset: be more explicit about available status * reset: use legal macros * debug: fix macros * debug: of vs to * reset: unavailable vs unavail * havereset: unspecified behavior when dmactive low
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- Nov 17, 2017
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Tim Newsome authored
Refer to ISA and priv docs.
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mwachs5 authored
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Megan Wachs authored
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Tim Newsome authored
* Explain cache coherency wrt to system bus access I suspect we'll have to do something for systems that don't implement the Program Buffer, but let's get this ball rolling at least. Issue #140 * fences aren't guaranteed to affect caches. * Make description more abstract. Only refer to caches in a parenthetical.
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- Nov 16, 2017
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Tim Newsome authored
Issue #115
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- Nov 04, 2017
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Tim Newsome authored
Add an index to the document.
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Tim Newsome authored
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- Nov 03, 2017
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Tim Newsome authored
Also turn all register fields into hyperlinks to their definition. Hopefully this is enough to satisfy #142.
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- Oct 30, 2017
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Megan Wachs authored
* DM: Add hasreset and hasreset ack bits to DM Registers. Move other newly added fields to more aligned locations. * Debug Module: Add explanation for hasreset * hasreset clarifications * More clarifications for hasreset * hasreset typo (cleared 'by') * hasreset: Move dmerr and put impebreak back where it was * hasreset: more clarifications * HasReset : Renamed to "Have Reset" * havereset: unnecessary 'the' * Update debug_module.tex * spaces not tabs * space not tabs * havereset: Rename the ack bit to be more clear that it is acking the havereset, not that it has some quality * hasreset: Update PDF
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- Oct 26, 2017
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Tim Newsome authored
haltreq, resumereq, hartreset are per-hart bits
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Megan Wachs authored
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Tim Newsome authored
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- Oct 25, 2017
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Megan Wachs authored
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Megan Wachs authored
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Megan Wachs authored
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- Oct 20, 2017
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Tim Newsome authored
Include pdf.
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- Oct 19, 2017
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Tim Newsome authored
Fixes #166.
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Megan Wachs authored
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Tim Newsome authored
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- Oct 13, 2017
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Tim Newsome authored
Add \Fimpebreak, to support of implicit ebreak.
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- Oct 12, 2017
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Megan Wachs authored
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