Back-port from trunk to 2.31.1

	ld/
	* emulparams/elf32lriscv-defs.sh (DATA_START_SYMBOLS): New.
	(SDATA_START_SYMBOLS): Define __SDATA_BEGIN__.  Don't define
	__global_pointer$.
	(OTHER_END_SYMBOLS): New.  Define __global_pointer$.
	* testsuite/ld-riscv-elf/pcrel-lo-addend-2.d (#ld): Add --no-relax.

	bfd/
	* elfnn-riscv.c (riscv_elf_size_dynamic_sections): In dynobj->sections
	loop, handle htab->sdyntdata section.

The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.

	bfd/
	* elfnn-riscv.c (riscv_init_pcgp_relocs): Add explanatory comment.
	(riscv_free_pcgp_relocs, riscv_record_pcgp_reloc): Likewise.
	(riscv_find_pcgp_hi_reloc, riscv_reocrd_pcgp_lo_reloc): Likewise.
	(riscv_find_pcgp_lo_reloc): Likewise.
	(riscv_delete_pcgp_hi_reloc, riscv_use_pcgp_hi_reloc): Delete.
	(riscv_delete_pcgp_lo_reloc): Likewise.
	(_bfd_riscv_relax_pc): Don't call riscv_use_pcgp_hi_reloc. Replace
	calls to riscv_delete_pcgp_lo_reloc and riscv_delete_pcgp_hi_reloc
	with TRUE.  Mark abfd arg as ATTRIBUTE_UNUSED.

	bfd/
	* elfnn-riscv.c (riscv_make_plt_header): New arg output_bfd.  Change
	return type to bfd_boolean.  If	EF_RISCV_RVE call _bfd_error_handler
	and return FALSE.  Return TRUE at end.
	(riscv_make_plt_entry): Likewise.
	(riscv_elf_finish_dynamic_symbol): Update call to riscv_make_plt_entry.
	(riscv_elf_finish_dynamic_sections): Update call to
	riscv_make_plt_header.

	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_pc) <R_RISCV_PCREL_LO12_I>: New local
	hi_sec_off which is symbol address with addend subtracted.  Use in
	riscv_find_pcgp_hi_reloc and riscv_record_pcgp_lo_reloc calls.

	bfd/
	* elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Add check for reloc
	overflow with addend.  Use reloc_dangerous instead of reloc_overflow.
	Add strings for the two errors handled here.
	(riscv_elf_relocate_section) In case R_RISCV_PCREL_LO12_I, rewrite
	comment.  Only give error with addend when used with section symbol.
	In case bfd_reloc_dangerous, update error string.

	ld/
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run pcrel-lo-addend-2.
	* testsuite/ld-riscv/elf/ld-riscv-elf/pcrel-lo-addend-2.d: New.
	* testsuite/ld-riscv/elf/ld-riscv-elf/pcrel-lo-addend-2.s: New.
	* testsuite/ld-riscv/elf/ld-riscv-elf/pcrel-lo-addend.d: Update name
	and error string.

2018-09-19  Kito Cheng  <kito@andestech.com>
ld/
	* emulparams/elf32lriscv.sh: Correct the library search path.
	* emulparams/elf32lriscv_ilp32.sh: Likewise.
	* emulparams/elf32lriscv_ilp32f.sh: Likewise.

2018-09-17  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/bge.d: New.
	* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
	  bleu.

2018-08-31  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/c-fld-fsd-fail.d: New.
	* testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise.
	* testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
	compressed floating point instructions.

2018-08-29  Kito Cheng  <kito@andestech.com>

gas/
	* config/tc-riscv.c (riscv_subset_supports): New argument:
	xlen_required.
	(riscv_multi_subset_supports): New function, able to check more
	than one extension.
	(riscv_ip): Use riscv_multi_subset_supports instead of
	riscv_subset_supports.
	(riscv_set_arch): Update call-site for riscv_subset_supports.
	(riscv_after_parse_args): Likewise.

include/
	*opcode/riscv.h (MAX_SUBSET_NUM): New.
	(riscv_opcode): Add xlen_requirement field and change type of
	subset.

opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
	riscv_opcode.xlen_requirement.
	* riscv-opc.c (riscv_opcodes): Update for struct change.

	gas/
	2018-08-23  Kito Cheng  <kito@andestech.com>
	* config/tc-riscv.c (arg_lookup): Checking
	length before look up.
	* testsuite/gas/riscv/fence-fail.d: New file.
	* testsuite/gas/riscv/fence-fail.l: Likewise.
	* testsuite/gas/riscv/fence-fail.s: Likewise.
	* testsuite/gas/riscv/rouding-fail.d: Likewise.
	* testsuite/gas/riscv/rouding-fail.l: Likewise.
	* testsuite/gas/riscv/rouding-fail.s: Likewise.

	bfd/
	* elfnn-riscv.c (riscv_elf_create_dynamic_sections): For .tdata.dyn,
	add SEC_LINKER_CREATED flag.

	include/
	* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
	(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
	(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.

	opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
	fields.
	* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.

	gas/
	* configure.tgt (riscv*): Accept as alias for riscv32*.

Fix typo in src-release.sh script.  Update French translation for gold and Spanish translation for ld.

gold	* po/fr.po: Updated French translation.
ld	* po/es.po: Updated Spanish translation.
.	* (DEVO_SUPPORT): Fix typo in previous delta.
	(do_proto_toplev): Add --quiet option to configure command line.

gold	PR gold/23409
	* symtab.cc (Symbol_table::define_special_symbol): Add check for
	version name on existing symbol.
	* testsuite/Makefile.am (ver_test_pr23409): New test case.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/ver_test_pr23409.sh: New test script.
	* testsuite/ver_test_pr23409_1.script: New version script.
	* testsuite/ver_test_pr23409_2.script: New version script.

	* src-release.sh (DEVO_SUPPORT): Add test-driver and ar-lib.

	* config/tc-arm.c (do_neon_mov): When converting an integer
	immediate into a floating point value, check that the conversion
	is valid.  Also warn if the immediate is valid as both a floating
	point value and a bit pattern.
	* testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use
	floating point bit patterns.
	* testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly
	of the new insns.

This is a followup to git commit 97196564 "Strip global symbol
defined in discarded section".  If a symbol defined in a discarded
section was dynamic, that patch left .dynsym with holes (ie. all zero
entries).  For example, the following from libstdc++.so:

Symbol table '.dynsym' contains 6090 entries:
   Num:    Value          Size Type    Bind   Vis      Ndx Name
     0: 0000000000000000     0 NOTYPE  LOCAL  DEFAULT  UND
     1: 00000000000a74e0     0 SECTION LOCAL  DEFAULT   10
     2: 0000000000264180     0 SECTION LOCAL  DEFAULT   17
     3: 0000000000000000     0 NOTYPE  WEAK   DEFAULT  UND _ITM_addUserCommitAction
     4: 0000000000000000     0 NOTYPE  WEAK   DEFAULT  UND _ITM_memcpyRtWn
     5: 0000000000000000     0 NOTYPE  LOCAL  DEFAULT  UND
readelf: Warning: local symbol 5 found at index >= .dynsym's sh_info value of 3
     6: 0000000000000000     0 NOTYPE  LOCAL  DEFAULT  UND
readelf: Warning: local symbol 6 found at index >= .dynsym's sh_info value of 3
[snip]

This patch removes the symbols from .dynsym too.

	PR 17550
	* elflink.c (_bfd_elf_fix_symbol_flags): Hide dynamic symbols
	in discarded sections.

(cherry picked from commit af0bfb9c)

This patch adds support for the SSBB and PSSBB speculation barrier instructions to the AArch64 assembler and disassembler.

For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf

opcodes	* aarch64-tbl.h (aarch64_opcode_table): Add entry for
	ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas	* testsuite/gas/aarch64/system.s: Add test for ssbb
	and pssbb.
	* testsuite/gas/aarch64/system.d: Update accordingly
	and remove explicit addresses.

opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
     csdb together with them.
     (thumb32_opcodes): Likewise.

gas  * config/tc-arm.c (insns): Add new ssbb and pssbb instructions.
     * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb.
     * testsuite/gas/arm/csdb.d: Likewise
     * testsuite/gas/arm/thumb2_it_bad.s: Likewise.
     * testsuite/gas/arm/thumb2_it_bad.l: Likewise.
     * testsuite/gas/arm/barrier.d: Update with ssbb.
     * testsuite/gas/arm/barrier-thumb.d: Likewise.

This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.

The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.

The list has been cross checked (by hand) through the Arm ARM version Ca.

opcodes/

	PR binutils/23192
	* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
	mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
	umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
	sqdmulh, sqrdmulh): Use Em16.

gas/

	PR binutils/23192
	* testsuite/gas/aarch64/illegal-by-element.s: New.
	* testsuite/gas/aarch64/illegal-by-element.d: New.
	* testsuite/gas/aarch64/illegal-by-element.l: New.

(cherry picked from commit 45a28947

)
Signed-off-by: Tamar Christina <tamar.christina@arm.com>

Resolved reference to a weak undefined symbol in PIE must not have
a dynamic relative relocation against itself, otherwise the value of a
reference will be changed from 0 to the base of executable, breaking
code like the following:

  void weak_function (void);
  if (weak_function)
    weak_function ();

This fixes tests for PR ld/22269 and a number of PIE tests in xtensa gcc
testsuite.

bfd/
2018-07-11  Max Filippov  <jcmvbkbc@gmail.com>

	* elf32-xtensa.c (elf_xtensa_allocate_dynrelocs): Don't allocate
	space for dynamic relocation for undefined weak symbol.
	(elf_xtensa_relocate_section): Don't emit R_XTENSA_RELATIVE
	relocation for undefined weak symbols.
	(shrink_dynamic_reloc_sections): Don't shrink dynamic relocation
	section for relocations against undefined weak symbols.

(cherry picked from commit c451bb34)

Reimport a patch to fix building gold on Cygwin64 systms: m.arena has size_t on Cygwin64 and thus errors out due to -Werror=format.

gold	* main.cc: Print m.arena as long long.

I just stumbled over this with 2.29.1 while building a cross-toolchain, on Cygwin64, but it's still the same for 2.30. m.arena has size_t on Cygwin64 and thus errors out due to -Werror=format.

gold
	* main.cc: Print m.arena as long long.