Commits · main · github.com / riscv / riscv-aclint

Jan 12, 2022
- Correct project in clone error. · 63422480
  Jeff Scheel authored Jan 11, 2022
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-Signed-off-by: Jeff Scheel <jeff@riscv.org>
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  63422480
- Additional details of failure mode · cebde1ff
  Jeff Scheel authored Jan 11, 2022
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Signed-off-by: Jeff Scheel <jeff@riscv.org>
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  cebde1ff
- Document use of submodules · fa58863f
  Jeff Scheel authored Jan 11, 2022
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Signed-off-by: Jeff Scheel <jeff@riscv.org>
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  fa58863f
May 16, 2021

Initial draft of the ACLINT specification · 8c08bc74

Anup Patel authored May 11, 2021



This patch adds initial draft of the ACLINT specification which
defines a MTIMER, MSWI and SSWI memory mapped devices.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

8c08bc74