Signed-off-by: Anup Patel <apatel@ventanamicro.com>

We have more dependencies after moving to common RISC-V international
theme so we update "install-debs" and "install-rpms" make targets
accordingly.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>

-Signed-off-by: Jeff Scheel <jeff@riscv.org>

Signed-off-by: Jeff Scheel <jeff@riscv.org>

Signed-off-by: Jeff Scheel <jeff@riscv.org>

Signed-off-by: Jeff Scheel <jeff@riscv.org>

Signed-off-by: Jeff Scheel <jeff@riscv.org>

The offset range in section heading of MSIP and SETSSIP registers
should not include reserved space. This patch fixes it.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Based on discussion on platform spec mailing list, we use the term
"MTIME tick period" instead of "MTIME update period and relax the
requirement on synchronization interval between multiple MTIME
registers.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We update PDF theme to show page number in footer of each page.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

When we have multiple MTIMER devices, the MTIMECMP registers of a
given MTIMER device should only compare against the MTIME register
of the same device.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We consistent way of referring MSIP nad SSIP bits of the
mip CSR.

Suggested-by: Greg Favor <gfavor@ventanamicro.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>

We should use asciidoc sidebar for non-normative text everywhere
hence we update MTIMER chapter accordingly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The patch re-writes the text describing read/write behaviour to
avoid any ambiguity for hardware implementations.

Suggested-by: Greg Favor <gfavor@ventanamicro.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>

The SSIP register name is misleading so let's rename it to
SETSSIP register so that the name explicitly states that
we can only set SSIP bit using this register but can't
clear SSIP bit using this register.

Suggested-by: John Hauser <jh.riscv@jhauser.us>
Signed-off-by: Anup Patel <anup.patel@wdc.com>

We don't need to change mip.SSIP bit definition in the RISC-V
privilege specification for ACLINT SSWI device instead the
signal from ACLINT SSWI device to the HART can be edge-sensitive
which will set the mip.SSIP bit in the HART and to clear the
mip.SSIP bit software can write 0.

Suggested-by: John Hauser <jh.riscv@jhauser.us>
Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We do minor updates to synchronizing multiple MTIME registers
and move it back as section of MTIMER chapter.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The MTIMER devices has separate base addresses for the MTIME
register and the MTIMECMP registers so we update MTIMER
register map accordingly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

A RISC-V platform can have a MTIMER device local to a HART cluster
while sharing the same physical MTIME register accross multiple
MTIMER devices (i.e. multiple HART clusters).

Signed-off-by: Anup Patel <anup.patel@wdc.com>

If a MTIMER device is not connected to any HART then it should only
have MTIME register and no MTIMECMP registers.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Each ACLINT devices assigns a HART index to the associated HARTs
so this patch adds text describing HART index.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The synchronization of multiple MTIMER devices is a broad topic
and deserves to have it's own chapter hence this patch. We also
update text to ensure all lines are within 80 characters width.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The "On reset" phrase used in context of MTIMER, MSWI, and SSWI
devices mean "On device reset" so we update text accordingly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The maximum offset of MSIP/SSIP register is 0x3FFC instead of 0x4FFC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

%s/synchnronizing/synchronizing
%s/functionaities/functionalities
%s/compatiblity/compatibility
%s/triggerred/triggered
%s/managment/management
%s/synchroinzation/synchronization
%s/writting/writing

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Fix the git warning 'No newline at end of file'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

We should explicitly specify how machine-level timer interrupt
of a HART is pending and cleared.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We further improve MTIME synchronization text as-per suggestions
received in meeting and mailing list.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

On some RISC-V platforms, the MTIME synchronization sequence will
need to be done a few times until MTIME adjustment (or delta)
becomes zero. Also, we need a "fence i, i" to order the reads
to various MTIME registers.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

It is possible to have multiple MTIMER devices on a RISC-V platform
so we add initial text on how to go about synchronizing multiple
MTIMER devices.

Signed-off-by: Anup Patel <anup.patel@wdc.com>