Used this test to confirm that
https://github.com/riscv-software-src/riscv-isa-sim/pull/1013 works
right.

Adjust test to work with that.

* Add EbreakTest.

Confirm correct behavior when somebody bakes an ebreak instruction into
their code.

* Forgot to commit ebreak.c

That way it can go into flash.

Otherwise, "make run" doesn't work.

It includes the name in quotes:
```* 2    Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main```

Just ignore that part.

Now it will give slightly more helpful output if it fails.

This feature lets you easily interact with the gdb after the test has
run to a certain point.

They used to set U, A, D, in intermediate page table entries which is no
longer allowed.

The tests don't confirm that the order actually changes, but at least
the code that does the work now is executed during the tests.

Disconnects from gdb, and then reconnects, making sure that didn't
change any of the registers.

This test will start passing when
https://github.com/riscv/riscv-openocd/pull/661 merges.

Useful for estimating interactive performance.

It's not an argument to spike anymore.

Also switch testing the vector unit from multi-gdb to `-rtos hwthread`.
This exposes a bug in OpenOCD (which is already fixed).

Thanks to @pdonahue-ventana for pointing this out

...since not all implementations will support it

Fixes #350

1. Don't run all tests in multi-spike. Extra coverage is negligible, and
it just takes too long.
2. Increase a few timeouts.

There are two reasons that writing the cycle counter might trap:
- Because it's a read-only CSR
- Because mcounteren.CY=0 or scounteren.CY=0

We want to make sure we're testing the first property, so set up
the other bits accordingly.

Added "#define stvec mtvec" under __MACHINE_MODE ifdef.

Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>

illegal.S:
- After the test enters supervisor mode, check if paging is supported.
- If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following:
-- SFENCE.VMA causing illegal instruction trap regardless of TVM.
-- Access to SATP does not trap.
-- Jump to the same TSR check as regular S-mode
-- End test

sbreak.S & scall.S:
- Before checking for scause, check if the core is in CLIC-mode (mtvec[1]).
- If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value.
- Otherwise, don't mask off any scause bits as in the original test.

Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>

* Test debugging multiple spikes in a daisy chain.

* Hugely speed up rbb_daisychain.

Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.

* WIP

* Test daisy chained homogeneous spike instances.

For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.

* Enable Sv48Test.

Didn't mean to disable it with this commit.

* Test authentication again.

Another change I hadn't meant to push...

* Add FreeRTOS smoke tests.

Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.

* Also test `-rtos FreeRTOS`.

It's faster to figure out there that the test is going to N/A.

Resolves #323

Otherwise, we get infinite recursion.

Resolves #321
Resolves #322

* Bump riscv-test-env

* Merge master

* Don't assume that mscratch is initialized to a particular value on reset

* Remove testcase that relies on the implementation-specific WFI time limit being 0.

This allows the vast majority of these tests to work with compilers that
don't support the V extension yet, which is helpful for people who
aren't using a vector branch of the compiler.

Specifically, this will hopefully allow us to run regression tests
against OpenOCD on every change, per
https://github.com/riscv/riscv-openocd/pull/563.

This fixes an intermitten failure when running these tests.

As of tomorrow that feature is officially no longer supported in
OpenOCD, so stop testing it.

- After discussion in riscv/riscv-tests#315, disable this test case, as it
  makes implementation assumptions which are not valid with respect to the
  specification.

- Leave code present but commented out.

 On branch dev/benm-disable-lrsc-test-4
 Changes to be committed:
	modified:   isa/rv64ua/lrsc.S

HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.