Also fix bug in parsing nan.

3a98ec2e introduced a subtle bug because
of the value of TESTNUM at the point an expected exception was taken.  Fix
by moving the new tests earlier in the program.

* WIP

* Add vector register smoketest.

Also redo the gdb value parsing code to accommodate the more complicated
way that vector registers look.

* Test vector access a little more thoroughly.

* Revert unnecessary changes.

This way if you end up reading a value that you suspect might be coming
from another hart/register, you can clearly see where it came from.

If it's in the path, at least. This way you get human readable assembly
in the log instead of hex values.

Solves https://github.com/riscv/riscv-tests/issues/241 : Each mhartid has the same size of stack & TLS. (#242)

Added CSR test cases on whether writing 0 to CSR works, as that might get overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)

This catches more corner cases where this may be a problem.

* WIP

* Smoke test virtual address support.

Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as
large as possible pages to 1:1 map the rest of RAM so those sizes do get
minimal coverage as well.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

`make` now takes 31s, `make all` takes 1m53s.
The new CheckMisa test ensures that the misa value specified in the
configuration is correct.

The symbols used to query the size of .tdata and .tbss need not be
thread-local themselves; instead, make them linker script-provided
non-thread-local symbols.

* Improve parallellism in debug test Makefile

Now each test is an individual make target, so you can get the most out
of however many cores you have. On my 12-core system, `make` went from
2m45s to 42s, and `make all` went from `3m25s` to `2m39s`.

If you have few cores, this change may actually slow things down a bit,
because ExamineTarget is run for every gdbserver.py invocation.

* Remove test target.

This binary comes from
https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2,
which will hopefully be accepted upstream.

The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.

This test checks that an I$ appears to be physically indexed.

* Parse inf/nan floats.

* Enable mstatus.fs in SimpleF18Test

Also accept "unable to fetch" message when FPRs aren't supported.

* Add config files for HiFive Unleashed.

* Add configs to flash HiFive Unleashed.

All tests pass.

The latest OpenOCD doesn't need (nor support) this anymore.

Hopefully this is enough information that I can simply point people who
submit OpenOCD changes to it, and they can run the tests themselves.

Instead of relying on $RISCV.  Using $RISCV was common in the early
days, but nowadays many tools are simply installed alongside the rest of
the system.

* Let the debugger enable mstatus.F if necessary.

* Ignore (some) gdb debug output.

* Increase timeout.

* Make newer version of pylint happy.

* Let the debugger enable mstatus.F if necessary.

* Ignore (some) gdb debug output.

* Increase timeout.

* Make newer version of pylint happy.

* Parse floats the way mainline gdb prints them.

For 64-bit floats, it shows both float and double results. Now more
tests pass using mainline gdb.

* Disable ANSI when talking to gdb.

Helps more tests pass with mainline gdb.

* Parse {float=...,double=...} in "info registers"

Makes tests work better with mainline gdb.

Also work with the new command line options that were renamed in
https://github.com/riscv/riscv-isa-sim/pull/299