Added "#define stvec mtvec" under __MACHINE_MODE ifdef.

Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>

illegal.S:
- After the test enters supervisor mode, check if paging is supported.
- If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following:
-- SFENCE.VMA causing illegal instruction trap regardless of TVM.
-- Access to SATP does not trap.
-- Jump to the same TSR check as regular S-mode
-- End test

sbreak.S & scall.S:
- Before checking for scause, check if the core is in CLIC-mode (mtvec[1]).
- If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value.
- Otherwise, don't mask off any scause bits as in the original test.

Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>

* Test debugging multiple spikes in a daisy chain.

* Hugely speed up rbb_daisychain.

Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.

* WIP

* Test daisy chained homogeneous spike instances.

For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.

* Enable Sv48Test.

Didn't mean to disable it with this commit.

* Test authentication again.

Another change I hadn't meant to push...

* Add FreeRTOS smoke tests.

Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.

* Also test `-rtos FreeRTOS`.

It's faster to figure out there that the test is going to N/A.

Resolves #323

Otherwise, we get infinite recursion.

Resolves #321
Resolves #322

* Bump riscv-test-env

* Merge master

* Don't assume that mscratch is initialized to a particular value on reset

* Remove testcase that relies on the implementation-specific WFI time limit being 0.

This allows the vast majority of these tests to work with compilers that
don't support the V extension yet, which is helpful for people who
aren't using a vector branch of the compiler.

Specifically, this will hopefully allow us to run regression tests
against OpenOCD on every change, per
https://github.com/riscv/riscv-openocd/pull/563.

This fixes an intermitten failure when running these tests.

As of tomorrow that feature is officially no longer supported in
OpenOCD, so stop testing it.

- After discussion in riscv/riscv-tests#315, disable this test case, as it
  makes implementation assumptions which are not valid with respect to the
  specification.

- Leave code present but commented out.

 On branch dev/benm-disable-lrsc-test-4
 Changes to be committed:
	modified:   isa/rv64ua/lrsc.S

HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.

This test would have found
https://github.com/riscv/riscv-openocd/issues/559.

* Refactored rv64ud structural test to use pass/fail macros and test numbers

* More clean up so test actually jumps to fail label

Resolves #303

* ext: add zfh extension test case and related macro

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* build: add zfh to target

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Addresses #289.

This is now required to use `-rtos riscv`.
Addresses the aside mentioned in #287.

Make sure OpenOCD cooperates when a user sets a trigger by writing
tselect/tdata* directly.

* WIP

* WIP

* Vector test seems to work well with spike.

* Check a0 in case the program didn't work right.

* Return not applicable if compile doesn't support V

* Add a basic semihosting test.

* Need to configure semihosting on each target.

* WIP

* Parse "cannot insert breakpoint" message.

Also use sys.exit instead of exit, per new pylint's suggestion.

Also use sys.exit instead of exit, per new pylint's suggestion.

Test the behavior described in
https://github.com/riscv/riscv-openocd/issues/76.