Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

This PR adds issue queue modeling to Olympia, by allowing users to
define the number of issue queues, which execution units map to which
issue queues, and which target pipes are supported for each execution
unit.

Regressions will fail until we merge [scoreboard
fix](https://github.com/sparcians/map/pull/468

) in Sparta.
Old flow:
dispatch -> executepipe->execute

New flow:
dispatch -> issue queue -> executepipe -> execute

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>

This isolates the Fusion API from the domain specific language.

After an agreement on syntax the DSL would be added as an improvement to
the API.

---------

Co-authored-by: Jeff Nye <jeff@www.condorcomputing.com>

This SHA is an example of how to generate PEvents (Performance Events)
typically used for correlation
efforts between a perf model and hardware.

PEvents are a more "compact" form of the pipeout collection pairs,
allowing a modeler to specify more direct items
for collection. Pipeout pairs can be more elaborate/detailed. However,
with some clever coding, there can be
reuse -- it's not done here.

To generate performance events, use the command line parameter
`--pevents <filename> <pevent1,pevent2,...|all>`.

Examples:
```
# All pevents
./olympia traces/dhry_riscv.zstf --pevents retire.out all -i100

# Just RETIRE pevent
./olympia traces/dhry_riscv.zstf --pevents retire.out RETIRE -i100

# RETIRE and COMPLETE pevent
./olympia traces/dhry_riscv.zstf --pevents retire.out COMPLETE,RETIRE -i100
```

While I was at it, I removed the generated annotation for pipeline
collection for LoadStore/MemoryAccess classes -- uses NVP which
generates faster, as well as creates smaller pipeouts.

---------

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

Improvements to Dromajo's STF tracing support require the latest version
of the STF library.

As part of #143 use MemoryAccessInfo as the standard transaction type
for making memory requests outside of the core, instead of instructions.

This paves way for adding an instruction cache, as well as prefetching
and more complicated memory subsystems where requests do not always
correspond to a particularly instruction.

Changes are minor, mostly just renaming.

Co-authored-by: Daniel Bone <daniel.bone@imgtec.com>

- Fix pipeline flush mechanisms by removing inflight instructions inside
functional units, recovering the rename map, and adding trace rewind
functionality
- Add FlushCriteria class for requesting flushes to and from the
FlushManager
- Update FlushManager to handle and arbitrate between multiple flush
sources
- Add flush request port from ExecutePipe to FlushManager intended to be
used for mispredicted branches
- Delay completing instructions in ExecutePipe by a cycle to fix execute
flush race conditions
- Add branch identification methods for Inst
- Add test to send random flushes from the branch unit

---------

Signed-off-by: danbone <daniel.d.bone@gmail.com>
Co-authored-by: Daniel Bone <daniel.bone@imgtec.com>

I noticed that the buffer empty termination checks weren't working as
intended.

Co-authored-by: Daniel Bone <daniel.bone@imgtec.com>

Signed-off-by: Lehua Ding <lehua.ding@rivai.ai>

This PR adds a notification from ROB to the entire simulation that the ROB
is about to or is expecting simulation to correctly terminate.  If a unit listens
for that notification, it can use that information to determine if simulation 
ended improperly, meaning, it might still have work to do, but didn't expect
simulation to stop.  An example of how this can happen: a unit is NOT 
scheduling an event to do work (a bug) because of a missed path to "wake"
it up.  

If the sparta::Scheduler ends simulation because it has no events to 
run, the unit will not receive the end-of-simulation notification from the ROB
and can throw an exception in this case.

---------

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
Co-authored-by: Knute Lingaard <klingaard@gmail.com>

This PR introduces the following
- Allows loads to perform Virtual address to Physical address
translation before older loads complete
  This can be configured using a parameter in the LSU (`allow_speculative_load_exec`)
- Allow non blocking cache lookup requests. Depends on #91 for the cache
to support this feature
- Implements Ready queue - simulator-only structure to speed up
instruction lookup in the LSU
- Mitigates data hazards introduced by instructions running out of order
- The length of the different stages of the LSU pipeline can be
configured through the parameters.

---------

Co-authored-by: Knute Lingaard <klingaard@gmail.com>

Unfortunately my editor removed a lot of superfluous white space which
makes this PR look big.

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

Added restrictions on supported programming languages

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

-> L2Cache can accept multiple requests from DCache and IL1.
-> Cache functional model used is SimpleDL1.
-> Configurable cache hit latency. 
-> Misses are forwarded to BIU and kept are tracked in the local buffer.
-> Miss to the pending cacheline is not sent out to BIU.
-> Backpressure handling for BIU credits.
-> make regress clean.

---------

Signed-off-by: Kunal-Buch <145377279+Kunal-Buch@users.noreply.github.com>
Co-authored-by: Knute <56927209+klingaard@users.noreply.github.com>

Fixed a couple of things:
1. Issue 126: bad character in ALF file generated from missing raw
string identifier for python: r"\1"
2. Added dependency in Makefile on the gen_alf.py script
3. Added error message when the MAP ALF generator cannot be found

Fix renaming to skip renaming of x0 outlined in
https://github.com/riscv-software-src/riscv-perf-model/issues/118

.

Changes:
- `renameInstructions_()` now checks if a source is x0, if it is and is
a data operand for a LSU operation, we still create a data register for
it, as we need to check in LSU for x0 before issuing instruction
- Added a boolean `x0` field to `Reg` struct in `RenameData` that tracks
if a data register is an `x0` instruction. This helps on reclamation of
rename credits in `getAckFromROB_()` to make sure we don't decrement for
an x0 data register
- Updated logic to handle for destination reclamation in
`getAckFromROB_()` to ensure when we reclaim credits/freelist
registers/references, we don't process them for x0 destinations
- Fixed initial allocation of freelist registers for `RF_INTEGER` to
only map registers for x1 - x31, before we were mapping from x0 - x31,
so we should technically see a performance improvement as we gained 1
extra freelist register from not renaming x0

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute <56927209+klingaard@users.noreply.github.com>

Removed the old perl generator; uses the new python generator in Sparta.

These changes make a few assumptions: 
1. The user is using a newer version of sparta map_v2
2. The path to the clone of map is next to the clone of olympia

improve performance when stf tracing is enabled, issue #55 
 
retain n_cycles=10000 until the stf trace opc is detected. 
Once the stop opc is detected restore n_cycles=10000

result is better interactivity under linux, improving overall
performance and usability when not actively generating a trace.

This is a re-implementation of previous draft PR.

trace opc trigger detection is done in dromajo_template.
trace record creation and handling is done in dromajo_stf.cpp
headers gathered into dromajo_stf.h

---------

Co-authored-by: jeff <jeffnye-gh@github.com>

Change name of the SimpleDL1 class to a more generic name "SimpleCache3"

Fixing https://github.com/riscv-software-src/riscv-perf-model/issues/116

First cut of applied Clang format and new build rules for it.  We will slowly move
each and every file over to the new formats.

---------

Co-authored-by: Knute Lingaard <sparcians1@gmail.com>

Does not work yet. DO NOT MERGE

---------

Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

Removed some dead code as well.

Added `void onStartingTeardown_() override {}` to the
LSU in this PR as an example. This method is called every time just
before the unit is destroyed -- either during an exception or a clean teardown.

Added new pipeline target: `f2i`. Fixed the JSONs to reflect the
intended source/dest direction.

Clang-format config based on the style guide in #87

---------

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

I kept the logic the same as it was earlier.
One of the design considerations was to use the BIU to communicate with
the cache and MMU.However it was later decided to keep the communication
simple until we design a more robust MMU design.

Same as #77 but the branch is in this repo instead of the fork

---------

Co-authored-by: vineethkm <vineethkm.01@gmail.com>
Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

The goal of the PR is to improve build times.
Currently the build steps take around > ~15 mins and most of the time is
spent building sparta and the other dependencies.
This should bring it down to roughly ~6 mins.

CCache is used to cache build files, the cache for each branch is unique
to prevent cache invalidation issues between different branches.

Conda dependencies are also cached although the time to build is not
affected as much roughly ~1 mins but would be higher if the network is
slow.Conda spends a lot of time checking the dependencies.

Cached action run
https://github.com/h0lyalg0rithm/riscv-perf-model/actions/runs/5987171626

Adds separate tracking address/data operands for stores
(https://github.com/riscv-software-src/riscv-perf-model/issues/69).
Fixes isStore bug
(https://github.com/riscv-software-src/riscv-perf-model/issues/78

).
Fixes assertion bug in LSU.

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>

This patchset adds documentation for generating coremark trace from
scratch.

Adding space after the message, as instruction details follow

Signed-off-by: avinash mehta <avinashmehtadelhi@gmail.com>

Addressing bug found in
https://github.com/riscv-software-src/riscv-perf-model/discussions/72

closes #64