Suppresses a warning on newer compilers for -std=c++20.

Use -iquote instead.  This prevents our include paths from messing up
the system headers depended upon by libstdc++.  (The specific problem
was syscall.h in fesvr/, which was interfering with libstdc++'s
dependence on the system's syscall.h for SYS_futex.)

Subproject headers can now be included in the following ways:

    #include "foo.h"      // for a header local to this subproject
    #include <bar/baz.h>" // for a header in another subproject

But no longer:

    #include <baz.h>      // for a header in any subproject

As a special case, libfdt needs itself to be added to the -I path,
because their coding style is to use angle brackets for local headers.

Upgrade Spike to compile with c++2a and use designated initializers

Fix help message to document `--device=<name>,<args>` usage by #1522

Update README.md

Fix c.mop.N decoding

Add missing prerequisite libboost-regex-dev

Signed-off-by: Katharina <KatCe@users.noreply.github.com>

Raise illegal instruction instead of virtual instruction on WFI when TW=1 and VTW=0 in VU-mode

The previous implementation raises virtual instruction on WFI when TW=1 in VU-mode. According to the recent discussion, we expect an illegal instruction exception in this case.

Reference: https://github.com/riscv/riscv-isa-manual/issues/1234

The c.mop.N only accepts rd={x1, x3, x5, x7, x9, x11, x13, x15}. The
previous implemention incorrectly accepts additional rd={x17, x19, x21,
x23, x25, x27, x29, x31}.

Reduce NS16550 address space size to one page

..rather than unbounded, as it used to be.  This led to the rather
surprising issue #1600, where a part of the address space assumed to be
vacant would allow a subset of accesses.

Teach Sstc to respect xenvcfg.STCE

Fix hvip.VSEIP and hvip.VSTIP so they don't observe platform-specific interrupts

The H extension defines that bits VSEIP, VSTIP, and VSSIP of hvip are
writable. (The other bits of hvip are read-only 0.) Only hip.VSSIP
(mip.VSSIP) is an alias of hvip.VSSIP. The hip.VSEIP is the logical-OR
of hvip.VSEIP, selected bit of hgeip by hstatus.VGEIN, and
platform-specific external interrupt signals to VS-level, e.g., from
AIA. The hip.VSTIP is the logical-OR of hvip.VSTIP and platform-specific
timer interrupt signals to VS-level, e.g., from Sstc. Thus, the read
values of hvip.VSEIP and hvip.VSTIP differ from the ones of hip.VSEIP
and hip.VSTIP (mip.VSEIP and mip.VSTIP). In other words, the hvip isn't
an alias (proxy) of mip.

The current aliasing (proxy) implementation does not provide the desired
behavior for hvip.VSEIP and hvip.VSTIP. An ISA-level behavior difference
is that any platform-specific external and timer interrupt signals
directed to VS-level should not be observable through the hvip. For
instance, the hvip should not observe the virtual timer interrupt signal
from the vstimecmp CSR (Sstc extension), which isn't true in the current
implementation. Additionally, the hvip should not observe the virtual
external interrupt signal from the IMSIC device (AIA extension).
Another ISA-level behavior difference is that the hgeip and
hstatus.VGEIN also should not affect hvip.VSEIP, which isn't true in the
current implementation.

This commit fixes the issue by giving the hvip a specialized class,
hvip_csr_t. The hvip_csr_t aliases the hvip.VSSIP to the mip.VSSIP but
decouples the hvip.VSEIP and hvip.VSTIP from mip.VSEIP and mip.VSTIP.
Additionally, the commit updates the read value of mip to be the
logical-OR of hvip.VSEIP, hvip.VSTIP, and other sources.

When menvcfg.STCE=0, mip.STIP reverts to its defined behavior as if
unsupporting Sstc extension. When henvcfg.STCE=0, mip.VSTIP reverts
to its defined behavior as if unsupporting Sstc extension. [https://github.com/riscv/riscv-time-compare/issues/5]

The previous Sstc implementation does not respect the xenvcfg.STCE.
In other words, the Sstc may assert mip.STIP (mip.VSTIP) when
menvcfg.STCE=0 (henvcfg.STCE=0), which is a misbehaving.

Update trigger description in README.md

The number of triggers is configurable since https://github.com/riscv-software-src/riscv-isa-sim/pull/1219

.

The trigger description was for the limited implementation when developing the extension. All trigger types are supported now. The information isn't very useful anymore.

Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>

Much more readable and more maintainable.

Will allow access to designated initializers.

Use Ubuntu 20.04 for debug tests

This is what we do for the other CI tests.

vcpop.m, vfirst.m: delete unnecessary VSTART write.

zip and unzip of Zbkb require RV32

riscv: sim.cc: Consider cpu-map node in cpus node

Add missing log commit of mstatush

Fix vectored VS-level interrupts

They were going to the vector for cause 10 (VSEI) even though vscause
had been correctly translated to 9 (SEI).

Fixes #1340.

Signed-off-by: demin.han <demin.han@starfivetech.com>

Refactor put_csr to direct write

1. put_csr needs search
2. MSTATUS_MPV not written back for RV32

Signed-off-by: demin.han <demin.han@starfivetech.com>

Add unratified Zaamo and Zalrsc extensions

Signed-off-by: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>