This will also make it easier to support discontiguous hart IDs.

This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.

Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor.  In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.

The general strategy is to avoid iterating over the ID space.

Disallow negative hartids, repeated hartids, and empty lists.

Make htif->get_to/fromhost_addr methods public

Implement Zicond (conditional integer operations)

This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.

The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
 - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
 - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1

See
  https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.

Note this encoding.h's history is unusual because riscv-opcodes master
is currently incompatible with Spike.  See the PR that contains its
commit hash (https://github.com/riscv/riscv-opcodes/pull/157) and
discussion at https://github.com/riscv-software-src/riscv-isa-sim/pull/1234#discussion_r1092243338

Add icount trigger

triggers: if match triggers with both breakpoint exception and entering D-mode, then enter D-mode and ignore breakpoint exception

Add support for Svadu Extension

The addition of Svadu support and removal of --mmu-dirty
command line flag results in the dirty_enabled configuration state
no longer being used. Remove the remnants of this state.

With the addition of Svadu support, the --mmu-dirty flag
no longer controls behavior of A/D updates to PTEs. Remove
the flag.

The Svadu (https://github.com/riscv/riscv-svadu) extension updates
the A/D bits of PTEs:

1. In S/HS mode when menvcfg.hade=1
2. In G-stage page tables when menvcfg.hade=1
3. In VS mode when henvcfg.hade=1

To enable this behavior the 'svadu' ISA string is needed.

This newly added behavior supplants the --mmu-dirty flag. However,
that flag is not yet removed.

Add in the support for the HADE fields in menvcfg and henvcfg
based off of the svadu ISA string. This only allows for the writable
HADE bits being exposed when the svadu ISA string is employed. No
other behavior is implemented.

The Svadu extension adds a HADE field (bit 61) to both
menvcfg and henvcfg. Add the definitions so they can be utilized.

Make the ISA parser understand the Svadu extension.

Support all 64 PMP regions

No reason to check it both in sim_t::sim_t and in processor_t::set_pmp_num.

Add --triggers=n to control the number of supported triggers

Add htif_t tohost/fromhost accessors

Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>