- Nov 16, 2022
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YenHaoChen authored
Signed-off-by:YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
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YenHaoChen authored
Co-authored-by:
Tim Newsome <tim@sifive.com> Signed-off-by:
YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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Tim Newsome authored
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Tim Newsome authored
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Tim Newsome authored
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Tim Newsome authored
chain() -> get_chain() chain_bit -> chain
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Tim Newsome authored
dmode() -> get_dmode() trigger_t.dmode_bit -> mcontrol_t.dmode
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Tim Newsome authored
store() -> get_store() store_bit -> store
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Tim Newsome authored
load() -> get_load() load_bit -> bit
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Tim Newsome authored
execute() -> get_execute(), execute_bit -> execute
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YenHaoChen authored
structuralize trigger's tdata CSRs for modularization
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- Oct 21, 2022
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Andrew Waterman authored
Fix minor MMU bugs; clean up MMU some more
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Andrew Waterman authored
Fix tval reporting for CBOs; constrain cache-block sizes to reasonable values
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Andrew Waterman authored
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Andrew Waterman authored
mmu_t::translate may raise exceptions and so must be called with the original virtual address for tval to be set correctly.
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Andrew Waterman authored
16 B suffices to subsume all aligned accesses (including the Q extension). Spike does not actually rely on this property, but in some real systems, it is impractical to guarantee atomicity across cache lines. 4096 B suffices to prevent cache lines from spanning pages (which would require multiple TLB accesses). This one is a bug fix, since we were not performing multiple TLB accesses in this case.
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- Oct 20, 2022
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YenHaoChen authored
Only triggers.cc uses the arithmetic function cto(). Instead of putting the cto() in processor.h, putting it in arith.h with other arithmetic functions, e.g., ctz() and clz(), makes more sense.
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
Invoking refill_tlb to get the physical address is somewhat baroque, and not even helpful in practice, since successful SCs will fill the TLB anyway.
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Andrew Waterman authored
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Andrew Waterman authored
The last remaining use was LR, which we can identify through other means.
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Andrew Waterman authored
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise.
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Andrew Waterman authored
For now, preserve the macro for compatibility with existing uses.
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Andrew Waterman authored
For now, preserve the macro for compatibility with existing uses.
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Andrew Waterman authored
The earlier call to store_slow_path will catch the misalignment.
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Andrew Waterman authored
These are now only used by AMOs. Since AMOs are relatively uncommon, and since the slow path really isn't slow anymore, send them down the slow path to simplify the common case.
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Weiwei Li authored
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Weiwei Li authored
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Weiwei Li authored
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bluew authored
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