Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

See #617 for discussion.

Resolves #617.

Update config file to support aarch64

Check and use proc variable in MMU emulation

When deciding HS-mode interrupts in processor_t:take_interrupt()
we should use "~state.hideleg" instead of "~MIP_VS_MASK" because
VS interrupt bits are writeable in HIDELEG CSR.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We cannot blindly use proc variable in MMU emulation because external
debug emulation instantiates MMU with proc=NULL.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Misc fix 2020 12 14

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

When a single abstract command writes s0 and executes a program buffer
that leads to an exception, the value of s0 should still persist. The
fact that it did not masked the following bug in OpenOCD:
https://github.com/riscv/riscv-openocd/issues/559

Rvv fix 2020 12 04

ref:
  https://github.com/riscv/riscv-v-spec/commit/511d0b84a3848de437fd01990d078feaa2871b11



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Fix Issue #609 where extraneous debugging output was added when the user
invoked any simulation operation that involved addr_to_mem.

Add a core parameter to the interactive str command. This makes it
possible for the spike user to specify the device whose memory contains
the NUL-terminated string to be printed.

Fix hstatus.GVA and mstatus.GVA updation

We are saving new HTVAL value in wrong location for HTVAL CSR write
so let's fix this.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The hstatus.GVA and mstatus.GVA should be set only when guest virtual
address is written to stval or mtval CSRs at time of taking trap.

This patch update access, page fault, and guest page fault trap classes
so that we can pass gva flag correct from source of the trap.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

This patch fixes VSSTATUS bits updations as follows:
1. set_csr() should not allow writs to VSSTATUS.SD bit instead
   VSSTATUS.SD bit should be derived again after VSSTATUS is updated
2. set_virt() should copy FS, VS and XS bits when transitioning
   from virt=on (VS/VU-mode) to virt=off (HS/M-mode)

Signed-off-by: Anup Patel <anup.patel@wdc.com>

h/t @daniellustig

I verified the new versions still compile to efficient x86 code (rolw/bswap[q])

Pmp per core

The original implementation only uses the value in first core and apply it
to other core. The patch makes the configuration hetergeneous for differenct
cores.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

all atrribute in cpu could leverage it

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Broken by 91092f21948ba2e77bfbc4629b82b6aa14d5ed6