Fix processor_t:take_interrupt() for HS-mode interrupts (2aed3d24) · Commits · github.com / riscv-software-src / riscv-isa-sim

Commit 2aed3d24 authored Dec 18, 2020 by

Anup Patel Committed by Anup Patel Dec 18, 2020

Fix processor_t:take_interrupt() for HS-mode interrupts



When deciding HS-mode interrupts in processor_t:take_interrupt()
we should use "~state.hideleg" instead of "~MIP_VS_MASK" because
VS interrupt bits are writeable in HIDELEG CSR.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

parent 11389c9d

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