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riscv-software-src
riscv-isa-sim
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dynamic
2beafe8a
·
build: Dynamically link installed progs
·
Jul 09, 2023
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whole-archive
3f7cfa8a
·
build: Link spike binaries with --whole-archive
·
Jul 09, 2023
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zicond-default-disasm
37bef605
·
Disassemble Zicond by default
·
Jul 06, 2023
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unavailable
628820ef
·
Let debugger control hart availability
·
Jun 28, 2023
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check-overlap
31e915da
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Run 'make check' in CI
·
Jun 17, 2023
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remove-xbitmanip
45aeb8dd
·
Remove Xbitmanip from README
·
Jun 17, 2023
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devices
aa072a64
·
debug: Remove debug_module_t::add_device, its redundant
·
Jun 12, 2023
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rivosinc-etrigger_fix_exception_match
0e83fe66
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Call stash_privilege more selectively
·
May 18, 2023
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fix-bf16
84e2dca8
·
Add f64_to_bf16; fix f32_to_bf16
·
Apr 19, 2023
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rva-profile-support
54dd9179
·
WIP
·
Mar 30, 2023
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plic-clint-endian
456c9e19
·
Make clint tolerant of discontiguous hart IDs
·
Feb 05, 2023
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plctlab-plct-zce-fix2
c790cfd3
·
Contain C/Zc*-enable logic entirely within misa_csr_t
·
Feb 04, 2023
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speedup-hacks
4efafebe
·
tmp
·
Jan 11, 2023
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tmp
2cb5cf5d
·
For NS16550 UART, poll stdin less often
·
Jan 11, 2023
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itrigger-etrigger-cleanup
388753f9
·
Use ACTION_DEBUG_MODE instead of 1
·
Nov 15, 2022
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plic_uart_v1
68aeeb55
·
Merge branch 'master' into plic_uart_v1
·
Oct 17, 2022
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increase-stack-size
4b0e9c16
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Substantially increase context_t stack size
·
Sep 01, 2022
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debug_rom_fence
9e042c7b
·
Move fence inside entry_loop.
·
Jul 30, 2022
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trigger_priority
60ac4597
·
Simplify misaligned_load()
·
Jun 03, 2022
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simplify-misaligned
40cc0837
·
Actually inline load_fast/store_fast for clang/ARM
·
May 25, 2022
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