- Feb 15, 2022
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Anup Patel authored
We should disable IMSIC DT nodes in fdt_fixups() which are not accessible to the next booting stage based on currently assigned domain. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We add simple FDT irqchip driver for IMSIC so that generic platform (and other FDT based platforms) can utilize common IMIC library. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We add simple IMSIC library which is independent of hardware description format (FDT or ACPI). This IMSIC library can be used by custom OpenSBI platform support to setup IMSIC for external interrupts. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We can have IPIs based on external interrupts provided by devices such as AIA IMSIC so we should enable mie.MEIE bit at appropriate places in generic library. Signed-off-by:
Anup Patel <anup@brainfault.org> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We introduce nascent_init() platform callback which will allow platforms to do very early initialization of platform specific per-HART CSRs and per-HART devices. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We can have multiple FDT irqchip drivers to be probed when a RISC-V system has different types of interrupt controller in a hierarchy. This will be certainly the case when a RISC-V system has both RISC-V AIA IMSIC and RISC-V AIA APLIC implemented. We extend simple FDT irqchip framework to allow multiple FDT irqchip drivers to be used for same RISC-V platform. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
This patch adds sbi_trap_set_external_irqfn() API which can be used by OpenSBI platform code to set a callback function for external interrupts. The RISC-V AIA IMSIC driver will use this API to implement inter-processor interrupts on-top-of MSIs. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We should use AIA CSRs to process local interrupts whenever AIA is available. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
We extend HART feature detection to discover AIA CSRs at boot-time. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
The RISC-V AIA specification improves handling of per-HART local interrupts in a backward compatible manner. This patch adds defines for the new RISC-V AIA CSRs. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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- Feb 04, 2022
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Jakub Luzny authored
Previously, it was rounded down and that gives suboptimal results when non-standard clock sources or baud rates are used. Signed-off-by:
Jakub Luzny <jakub.luzny@codasip.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Petro Karashchenko authored
In a systems that provide strings.h and it is included together with sbi_bitops.h the compilation error appears. The ffs() and fls() are provided by strings.h Signed-off-by:
Petro Karashchenko <petro.karashchenko@gmail.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Aurelien Jarno authored
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: CC lib/sbi/sbi_tlb.o <<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages: <<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i' make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1 The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that. Signed-off-by:
Aurelien Jarno <aurelien@aurel32.net> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Tested-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Atish Patra authored
Currently, the mhpmevent CSRs are untouched during hart init during cold/warm boot. Ideally, we should clear out all the bits except overflow and MINH bit. That is required to disable overflow interrupt and inhibit counting in M-mode to avoid any spurious interrupts before perf start. Signed-off-by:
Atish Patra <atishp@rivosinc.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Atish Patra authored
PMU overflow interrupt should be disabled durinig initial configuration of counters. They should be enabled while starting counters. Fixes: 730f01bb ("lib: sbi: Support sscofpmf extension in OpenSBI") Signed-off-by:
Atish Patra <atishp@rivosinc.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Atish Patra authored
The counter mapping in DT may be incorrect if all the counters specified in the mapping are actually not physically present in the hardware. OpenSBI should only keep a mapping of counters enabled in hardware and defined in DT. This assume that all the programmable hpmcounters are consecutive as it doesn't make sense to build a system with sparse hpmcounters. Signed-off-by:
Atish Patra <atishp@rivosinc.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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- Jan 22, 2022
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Jukka Laitinen authored
Using "void *" in arithmetic causes errors with strict compiler settings: "error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]" Avoid these by calculating on "char *" where 1-byte data size is assumed. Signed-off-by:
Jukka Laitinen <jukkax@ssrc.tii.ae> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Aurelien Jarno authored
When the watchdog is running the HiFive Unmatched board does not reboot properly and shuts down itself a few seconds after reboot, in the early stages of the u-boot loading. On a Linux kernel this happens when the da9063_wdt module is loaded. This does not happen if the module is unloaded before reboot or if the watchdog module is loaded with "stop_on_reboot=1". Fix that by stopping the watchdog before attempting to reset the board. This is done by zeroing the TWDSCALE field of CONTROL_D register, unless it was already set to 0. Reported-by:
Tianon Gravi <tianon@debian.org> Signed-off-by:
Aurelien Jarno <aurelien@aurel32.net> Reviewed-by:
Nikita Shubin <n.shubin@yadro.com> Tested-by:
Nikita Shubin <n.shubin@yadro.com> Reviewed-by:
Anup Patel <anup@brainfault.org>
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Aurelien Jarno authored
da9063_reset() and da9063_shutdown() take the chip address in argument (like similar functions), but in practice use the da9063 global struct instead. Fix that. Signed-off-by:
Aurelien Jarno <aurelien@aurel32.net> Reviewed-by:
Nikita Shubin <n.shubin@yadro.com> Reviewed-by:
Anup Patel <anup@brainfault.org> Reviewed-by:
Xiang W <wxjstz@126.com>
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- Jan 11, 2022
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Anup Patel authored
Some of RISC-V emulators provide HTIF at fixed base address so for such emulators users have to hard-code HTIF base address in the linker script. To address this problem, we let users optionally provide fixed HTIF base address via platform support (or device tree). Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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Anup Patel authored
Currently, the ACLINT MSWI size check is forcing size to be at least 0x4000. This is inappropriate check because most systems will never utilize full 16KB for a single ACLINT MSWI device so instead we should check that ACLINT MSWI size is enough for on the associated HARTs. Signed-off-by:
Anup Patel <apatel@ventanamicro.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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- Dec 24, 2021
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Anup Patel authored
This patch updates OpenSBI version to 1.0 as part of release preparation. Signed-off-by:Anup Patel <anup.patel@wdc.com>
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- Dec 23, 2021
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Anup Patel authored
Some of the external firmwares using OpenSBI as library are facing issues with the weak memcpy() and memset() aliases in libsbi.a so we move these to fw_base.S. This way mapping of implicit memcpy() or memset() calls to sbi_memcpy() or sbi_memset() will only be done for OpenSBI firmwares. (Refer, https://github.com/riscv-software-src/opensbi/issues/234 ) In addition, we also add memmove() and memcmp() mappings in fw_base.S because as-per the GCC documentation the freestanding environment must provide memcpy(), memmove(), memset(), and memcmp(). Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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- Dec 22, 2021
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Heinrich Schuchardt authored
pmpcfg_csr and pmpcfg_shift are only negative for an unexpected value of __riscv_xlen. We can immediately return in this case. Signed-off-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Dec 16, 2021
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Xiang W authored
The commit 69d7e536 disables the -m(no-)save-restore option for clang, but clang11 supports this option. This patch uses the output information of the compiler to check whether the compiler supports this option. Signed-off-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Dec 11, 2021
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Anup Patel authored
When compiling with -Os option along with -ffreestanding, both GCC and clang will add implicit calls to memcpy() and memset() for stack variables initialized in declaration. The C standard as per Clause 4, the compiler cannot necessarily assume that anything beyond: * float.h * iso646.h * limits.h * stdalign.h * stdarg.h * stdbool.h * stddef.h * stdint.h * stdnoreturn.h * fenv.h * math.h * and the numeric conversion functions of stdlib.h. This patch maps memcpy() and memset() as weak-alias of sbi_memcpy() and sbi_memset() respectively so that implicit calls to memcpy() and memset() will compile properly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Xiang W <wxjstz@126.com>
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Anup Patel authored
The riscv target of CLANG-10 (or lower) does not support the -m(no-)save-restore option so we get compile warnings. This patch fixes compile warning by using -m(no-)save-restore option only for GCC. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn>
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Nikita Shubin authored
We should check if SSCOF extension is present, before applying inhibit mask and clearing overflow, otherwise undesirable value can be written in MHPMEVENT_N CSR. Signed-off-by:
Nikita Shubin <n.shubin@yadro.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Xiang W <wxjstz@126.com>
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Tsukasa OI authored
This commit makes Spike usable as QEMU (in fact, those are based on QEMU examples). Signed-off-by:
Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Dec 03, 2021
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Vincent Chen authored
RISC-V privilege specification does not specify how to encode the event ID. Therefore, each platform is allowed to customize its own encoding rule. The common encoding methods are as follow, directly assigning a number to an event, or every bit in the mphmevent CSR controls one specified event or mixes the above two methods. To enable OpenSBI to support the above three encoding methods simultaneously, this patch repurpose the dt property "riscv,raw-event-to-mhpmcounters". The "riscv,raw-event-to-mhpmcounters" will describes the one or multiple raw events that could be counted by a set of counters. But, the column number of "riscv,raw-event-to-mhpmcounters" is extended from 2 to 3. The 1st column (64bit) is the ID of the raw events. The 2nd column (64bit) represents a select_mask now to represent the bits used for event ID encoding. If a platform directly encodes each raw PMU event as a unique ID, the value of select_mask will be 0xffffffff_ffffffff. Signed-off-by:
Vincent Chen <vincent.chen@sifive.com> Signed-off-by:
Atish <Patra<atishp@rivosinc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Dec 02, 2021
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Jessica Clarke authored
BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by:Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com>
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- Nov 30, 2021
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Dong Du authored
A recent commit (b28f0700 ) turns to read from CSR_MCOUNTINHIBIT after checking the SBI_HART_HAS_MCOUNTINHIBIT HART feature, which leaves the mctr_inhbt uninitialized in pmu_ctr_find_hw(). As a result, compiler will complain: error: 'mctr_inhbt' may be used uninitialized in this function. This commit resolves the issue by assigning an initial value to mctr_inhbt. Signed-off-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Nikita Shubin authored
Fix missing space in sbi_hart_pmp_configure error printing. Signed-off-by:
Nikita Shubin <n.shubin@yadro.com> Reviewed-by:
Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by:
Xiang w <wxjstz@126.com>
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- Nov 23, 2021
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Vagrant Cascadian authored
Fix a spelling typo in error print. Signed-off-by:
Vagrant Cascadian <vagrant@debian.org> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Xiang W <wxjstz@126.com>
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- Nov 18, 2021
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Gabriel Somlo authored
Add support for the UART provided by the LiteX SoC framework (https://github.com/enjoy-digital/litex ), based on its FDT info (described in the Linux tree at Documentation/devicetree/bindings/serial/litex,liteuart.yaml). Signed-off-by:
Gabriel Somlo <gsomlo@gmail.com> Reviewed-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Nov 12, 2021
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Xiang W authored
We should clear A bits in prot variable before enabling A_NA4 or A_NAPOT. Signed-off-by:
Xiang W <wxjstz@126.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Nikita Shubin authored
da9063 PMIC can be used to reset/shutdown the Sifive Unmatched board. shutdown is done simply by writing SHUTDOWN bit to DA9063_REG_CONTROL_F register. reset via setting WAKEUP bit in DA9063_REG_CONTROL_F register followed by masking POWER and POWER1 domains and setting STANDBY bit in DA9063_REG_CONTROL_A, originally discovered by Alexandre Ghiti on linux-riscv maillists. Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Tested-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Signed-off-by:
Nikita Shubin <n.shubin@yadro.com>
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Nikita Shubin authored
Minimum SiFive I2C driver to read/send bytes over I2C bus. This allows querying information and perform operation of onboard PMIC, as well as power-off and reset. Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Tested-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Signed-off-by:
Nikita Shubin <n.shubin@yadro.com>
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Nikita Shubin authored
FDT based I2C framework on the top of I2C library. The drivers are probed on demand by fdt_i2c_adapter_get function. Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Tested-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Signed-off-by:
Nikita Shubin <n.shubin@yadro.com>
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Nikita Shubin authored
Helper library to keep track of registered I2C adapters, identified by dts offset, basic send/read functions and adapter configuration (enable, set dividers, etc...). Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Tested-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Signed-off-by:
Nikita Shubin <n.shubin@yadro.com>
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