129: PLIC peripheral r=romancardenas a=romancardenas

Same as #125 (closing right now) but with a clean commit history. I've been playing around with this implementation and detected nice-to-have features and boring patterns that could be implemented using macros. Pointers to repos that are already working with it:

- [`e310x` PAC](https://github.com/greenlsi/e310x)
- [`e310x-hal` HAL](https://github.com/greenlsi/e310x-hal)
- [`hifive1` BSP](https://github.com/romancardenas/hifive1) with an illustrative [example](https://github.com/romancardenas/hifive1/blob/master/examples/interrupt.rs

)

Co-authored-by: Román Cárdenas <rcardenas.rod@gmail.com>

131: fix a typo r=romancardenas a=OccupyMars2025



Co-authored-by: OccupyMars2025 <31559413+OccupyMars2025@users.noreply.github.com>

127: Add FENCE.I instruction r=almindor a=rmsyn



Co-authored-by: rmsyn <rmsynchls@gmail.com>

128: Add FENCE instruction r=almindor a=rmsyn



Co-authored-by: rmsyn <rmsynchls@gmail.com>

123: Added clippy to the CI workflow r=almindor a=romancardenas

I've been working with this crate for a while and noticed that it didn't include clippy as part of the CI process. This PR checks that clippy does not trigger any warning for new contributions. I also ran `cargo clippy --fix` to "fix" the crate.

If you think this is useful, I can adapt other repos (e.g., riscv-rt or e310x). Cheers!

Co-authored-by: Román Cárdenas <rcardenas.rod@gmail.com>

122: release v0.10.1 with critical section bug r=dkhayes117 a=almindor

Release the critical section bugfix from #121 

Co-authored-by: Ales Katona <ales@katona.me>

121: fix critial section implementation r=dkhayes117 a=tfx2001

It should be `0b1000` rather than `0b100`. `Bit 2` is a reserved bit, and `Bit 3` is `MIE` that needs to be cleared.

![image](https://user-images.githubusercontent.com/19427212/212855746-7df197f1-5582-4844-a58e-6c7269d03b22.png

)


Co-authored-by: tfx2001 <tfx2001@outlook.com>

120: release v0.10.0 r=almindor a=almindor

Fixed #119 

Co-authored-by: Ales Katona <ales@katona.me>

117: fix atomicity of critical section, fixes #116 r=dkhayes117 a=almindor

This changes `SingleHartCriticalSection::acquire` to be done in an atomic way.

Fixes #116

NOTE: no changelog since it fixes a small bug on unreleased change

Co-authored-by: Ales Katona <ales@katona.me>

110: Add critical-section 1.0 implementation, fix multicore unsoundness. r=almindor a=Dirbaio

~~Requires #109~~

This adds a [critical-section](https://github.com/rust-embedded/critical-section) implementation for single-core chips, based on disabling all interrupts.

`interrupt::free` is is unsound on multicore systems because it only disables interrupts in the
current core. For multicore chips, a chip-specific critical section implementationis needed instead. Unsoundness is fixed by not returning the `CriticalSection` token.

This is a breaking change.

This is the riscv equivalent of https://github.com/rust-embedded/cortex-m/pull/447 and https://github.com/rust-embedded/cortex-m/pull/448





Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>

This is unsound on multi-hart because it only disables interrupts in the
current hart. For multi-hart chips, a chip-specific critical section implementation
is needed instead.

Unsoundness is fixed by not returning the `CriticalSection` token.

This is a breaking change.

113: bump version to v0.9.0 due to breaking changes r=Disasm a=almindor

As per discussion on https://github.com/rust-embedded/riscv/pull/112

 we want to release `v0.9.0` and yank `v0.8.1` since the removals were a breaking change.

Co-authored-by: Ales Katona <ales@katona.me>