mstatus: Support vector extension

riscv: add `mcounteren` in-memory update functions

Adds functions for updating the in-memory `Mcounteren` structure without
touching the CSR.

Allows manipulating all bitfields in-memory, and writing the entire
value back to the CSR at once.

Uses the new `bf_extract` helper for the `mcounteren` register.

Fix semihosting::debug::exit() on riscv64 QEMU targets.

QEMU's handler for REPORT_EXCEPTION (a.k.a. TARGET_SYS_EXIT in QEMU sources)
expects two arguments for 64-bit systems, including riscv64. In the event
that a second argument is not provided, QEMU takes an error path which does
*not* exit the simulation.

The net result is that semihosting::debug::exit() hangs on riscv64 qemu
simulation.

Provide the necessry extra paramater to the syscall so that exit now
works properly.

Note that the second parameter only affects the simulator exit code if
the first parameter is ApplicationExit, and we use ApplicationExit only
for successful exit, so we can simply hardcode 0 as second parameter. On
the error path we set first parameter to RunTimeErrorUnknown and QEMU
properly returns exit code 1 regardless of second parameter.

riscv: add `mcountinhibit` module

Adds the `riscv::register::mcountinhibit` module for the `mcountinhibit`
CSR.

fixup: riscv: fix `mstatus` test

Fixes the assignment in the `mstatus` unti tests.

Align jump targets to 4 bytes

We use unconditional jumps to reach these locations but I think the
RISC-V unconditional jump cannot express locations that are not aligned
to 4 bytes.

`riscv-rt`: Support for vectored mode interrupt handling

Add Mstatus helpers to allow setting fields in Mstatus

Also remove local bf_* helpers

Co-authored-by: rmsyn <117854522+rmsyn@users.noreply.github.com>

Allow `Mstatus` values to be directly written back to the CSR.

This adds a macro to generate `write(value:T)` function for writing a
structured value to a CSR.

And add a clarifying doc comment that this is an operation on Mstatus
values, not on the CSR itself.

Without needing to touch the CSR. This allows multiple changes in a
single register write.

`riscv`: register: fix target architecture conditional compilation

Uses `cfg(target_arch)` conditional compilation selectors for exported
macros, since `cfg` flags generated from `build.rs` are not present for
downstream users.

Implement Eq and PartialEq for Range and Permission

Tidy per-ext check-cfg flags

It's useful to be able to do equality tests for these for unit tests.

riscv: build: make `cfg` variables more robust

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Change which Cargo `CFG` environment variables are used to select the
custom `cfg` variables.

See
https://github.com/rust-embedded/riscv/pull/204#issuecomment-2094089195
for discussion.

`riscv`: register: exports macros for custom CSRs