1. Apr 11, 2024
    • Kito Cheng's avatar
      Handle multilib config correctly · e719bb7c
      Kito Cheng authored
      `--build-arch-abi` may give more than one arch/abi pair if multilib
      enabled, but we don't handle that well before...
      
      Before the patch:
      ```bash
      $ scripts/generate_target_board --sim-name riscv-sim --cmodel medlow \
        --build-arch-abi "rv32imac-ilp32 rv32imafdc-ilp32d rv64imac-lp64 rv64imafdc-lp64d" \
        --extra-test-arch-abi-flags-list ""
      riscv-sim/-march=rv32imac/-mabi=ilp32 rv32imafdc/-mcmodel=medlow
      ```
      
      After the patch:
      ```bash
      $ scripts/generate_target_board --sim-name riscv-sim --cmodel medlow \
        --build-arch-abi "rv32imac-ilp32 rv32imafdc-ilp32d rv64imac-lp64 rv64imafdc-lp64d" \
        --extra-test-arch-abi-flags-list ""
      riscv-sim/-march=rv32imac/-mabi=ilp32/-mcmodel=medlow riscv-sim/-march=rv32imafdc/-mabi=ilp32d/-mcmodel=medlow riscv-sim/-march=rv64imac/-mabi=lp64/-mcmodel=medlow riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow
      ```
      e719bb7c
  2. Apr 06, 2024
  3. Apr 05, 2024
  4. Feb 29, 2024
  5. Feb 01, 2024
  6. Dec 19, 2023
  7. Dec 13, 2023
  8. Dec 11, 2023
  9. Dec 08, 2023
    • Yanzhang Wang's avatar
      Add misaligned memory access for spike. · 72a1fc00
      Yanzhang Wang authored
      The spec does not forbid the misaligned memory access. And the gcc
      will generate vector load/store to access misaligned memory by
      default.
      
      Currently the QEMU supports this feature, so to support in spike
      is also make sense.
      
      Reference test case: gcc/gcc/testsuite/gcc.dg/vect/vect-align-1.c
      72a1fc00
  10. Dec 01, 2023
  11. Nov 30, 2023
    • Tsukasa OI's avatar
      Document prerequisite on testing · c3bb5cae
      Tsukasa OI authored
      pyelftools is required for a helper script.
      
      This commit adds basic installation guide to install pyelftools and
      removes "automatic installation" of pyelftools from Makefile.
      c3bb5cae
  12. Nov 28, 2023
    • Tsukasa OI's avatar
      Bump binutils to the true v2.41 release · a19f6714
      Tsukasa OI authored
      Due to multiple accidents while releasing GNU Binutils, version 2.41,
      there are multiple tags that are broken.
      
      The true commit representing the version 2.41 of GNU Binutils is
      the head of `binutils-2_41-release-point` branch.
      
      This commit partially reverts commit c7853bf3.
      a19f6714
    • Pan Li's avatar
      Add OR operator for option '--with-extra-multilib-test' · 7e6696a6
      Pan Li authored
      
      
      This patch allows you provide the flags in build flags array acts on arch-abi
      __respectively__, you can use ',' to separate them. For example:
      
      `rv64gcv-lp64d:--param=riscv-autovec-lmul=dynamic,--param=riscv-autovec-preference=fixed-vlmax`
      
      will be consider as two target boards same as below:
      
      ```
      riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
      riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
      ```
      
      However, you can also leverage AND(`:`), OR(`,`) operator together but the
      OR(`,`) will always have the higher priority. For example:
      
      `rv64gcv-lp64d:--param=riscv-autovec-lmul=dynamic:--param=riscv-autovec-preference=fixed-vlmax,--param=riscv-autovec-lmul=m2`
      
      will be consider as tow target boars same as below:
      
      ```
      riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
      riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
      ```
      
      Signed-off-by: default avatarPan Li <pan2.li@intel.com>
      7e6696a6
  13. Nov 27, 2023
  14. Nov 22, 2023
  15. Nov 21, 2023
  16. Nov 20, 2023
    • Kito Cheng's avatar
      Improve make report with extra test arguments · 0e5c4051
      Kito Cheng authored
      Recently we have add the capability to adding extra compilation options
      for running GCC testsuite, but it seems not handle well on the `make report`
      part, it will ignore extra compilation options, and then...combine
      multiple report together.
      
      Now it will put in two different line, and the extra compilation options
      will listed in follwoing line, here is example output here:
      
                     ========= Summary of gcc testsuite =========
                                  | # of unexpected case / # of unique unexpected case
                                  |          gcc |          g++ |     gfortran |
       rv64gc_zicfilp_zicfiss/  lp64d/ medlow |20350 /  3967 |10158 /  2583 |18374 /  3098 |
       rv64gc_zicfilp_zicfiss/  lp64d/ medlow |   86 /    19 |   15 /     9 |   51 /    51 |
       -static
      0e5c4051
  17. Nov 19, 2023
  18. Nov 17, 2023
    • Pan Li's avatar
      Cleanup debug code and allow empty input. · 47cd201f
      Pan Li authored
      
      
      Signed-off-by: default avatarPan Li <pan2.li@intel.com>
      47cd201f
    • Pan Li's avatar
      Extend semantic for option '--with-extra-multilib-test' · c1ec5800
      Pan Li authored
      
      
      The `--with-extra-multilib-test` take the format like below for now.
      
      "<arch>-<abi>-[code-model][;<arch>-<abi>-[code-model]*"
      
      This patch would like to extend the sematic to support additional buil
      options for each combination. Aka:
      
      "<arch>-<abi>-[code-model][:opts]*[;<arch>-<abi>-[code-model][:opts]*]*"
      
      opts can be one or more build options splited by ':'. For example as
      below:
      
      * --param=riscv-autovec-lmul=m1
      * --param=riscv-autovec-lmul=dynamic:--param=riscv-autovec-preference=fixed-vlmax
      
      Thus the full example of the option `--with-extra-multilib-test` will be:
      
      `rv64gcv_zvl128b-lp64d:--param=riscv-autovec-lmul=m1;rv64gcv_zvl256b-lp64d:-
      -param=riscv-autovec-lmul=dynamic:--param=riscv-autovec-preference=fixed-vlmax`
      
      Signed-off-by: default avatarPan Li <pan2.li@intel.com>
      c1ec5800
  19. Nov 16, 2023
  20. Oct 17, 2023
  21. Oct 13, 2023
  22. Oct 12, 2023