RISC-V: Add support for XCVbi extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>
  Nazareno Bruschi <nazareno.bruschi@embecosm.com>
  Lin Sinan

include/ChangeLog:
	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	  macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
          for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

gas/ChangeLog:
	* config/tc-riscv.c (validate_riscv_insn): Add the necessary
	  operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
	  for CORE-V.
	* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
	* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.

include/ChangeLog:
        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          macros for XCVbi.
        * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
          for XCVbi.
        (enum riscv_insn_class): Add the XCVbi instruction class.

ld/ChangeLog:
	* testsuite/ld-riscv-elf/cv-bi-beqimm.d: New test.
	* testsuite/ld-riscv-elf/cv-bi-beqimm.s: New test.
	* testsuite/ld-riscv-elf/cv-bi-bneimm.d: New test.
	* testsuite/ld-riscv-elf/cv-bi-bneimm.s: New test.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests.

opcodes/ChangeLog:
	* riscv-dis.c (print_insn_args): Add disassembly for new operand.
	* riscv-opc.c: Add XCVbi instructions.