RISC-V: Add support for XCVelw extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

        * doc/c-riscv.texi: Note XCVelw as an additional ISA extension
          for CORE-V.
        * testsuite/gas/riscv/cv-elw-fail.d: New test.
        * testsuite/gas/riscv/cv-elw-fail.l: New test.
        * testsuite/gas/riscv/cv-elw-fail.s: New test.
        * testsuite/gas/riscv/cv-elw-fail-march.d: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
        * testsuite/gas/riscv/cv-elw-fail-march.s: New test.
        * testsuite/gas/riscv/cv-elw-pass.d: New test.
        * testsuite/gas/riscv/cv-elw-pass.s: New test.

opcodes/ChangeLog:

        * riscv-opc.c: (riscv_opcode) Add event load instructions.

include/ChangeLog:

        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          instruction opcode macros.
        * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.