This PR adds definitions and 'frecipe' feature for FP approximation
intrinsics/builtins. In additions, this adds and complements relative
testcases.

`getauxval` depends on `libc.include.sys_auxv`

`getauxval` depends on `open/read/close` which are not built on arm32.
Remove `getauxval` for now.

In 21551951

, the
"system-headers-coverage" option has been added but not used in all
necessary places.

Potential reviewers: @gulfemsavrun @petrhosek

Co-authored-by: Manuel Kalettka <manuel.kalettka@kernkonzept.com>

This combines the previously posted patches with some additional work
I've done to more closely match MSVC output.

Most of the important logic here is implemented in
AArch64Arm64ECCallLowering. The purpose of the
AArch64Arm64ECCallLowering is to take "normal" IR we'd generate for
other targets, and generate most of the Arm64EC-specific bits:
generating thunks, mangling symbols, generating aliases, and generating
the .hybmp$x table. This is all done late for a few reasons: to
consolidate the logic as much as possible, and to ensure the IR exposed
to optimization passes doesn't contain complex arm64ec-specific
constructs.

The other changes are supporting changes, to handle the new constructs
generated by that pass.

There's a global llvm.arm64ec.symbolmap representing the .hybmp$x
entries for the thunks. This gets handled directly by the AsmPrinter
because it needs symbol indexes that aren't available before that.

There are two new calling conventions used to represent calls to and
from thunks: ARM64EC_Thunk_X64 and ARM64EC_Thunk_Native. There are a few
changes to handle the associated exception-handling info,
SEH_SaveAnyRegQP and SEH_SaveAnyRegQPX.

I've intentionally left out handling for structs with small
non-power-of-two sizes, because that's easily separated out. The rest of
my current work is here. I squashed my current patches because they were
split in ways that didn't really make sense. Maybe I could split out
some bits, but it's hard to meaningfully test most of the parts
independently.

Thanks to @dpaoliello for extensive testing and suggestions.

(Originally posted as https://reviews.llvm.org/D157547 .)

This ensures full compare coverage for certain special constants.

This catches an assertion in a recommit of
dc3faf0e

Previously, we hard-coded the cap on block visits inside the framework.
This
patch enables the caller to specify the cap in the APIs for running an
analysis.

In D144319, Clang tried to land a change that would cause some functions
that are not supposed to return nullptr to optimize better. As reported
in https://reviews.llvm.org/D144319#4203982, libc++ started seeing
failures in its CI shortly after this change was landed.

As explained in D146379, the reason for these failures is that libc++'s
throwing `operator new` can in fact return nullptr when compiled with
exceptions disabled. However, this contradicts the Standard, which
clearly says that the throwing version of `operator new(size_t)` should
never return nullptr. This is actually a long standing issue. I've
previously seen a case where LTO would optimize incorrectly based on the
assumption that `operator new` doesn't return nullptr, an assumption
that was violated in that case because libc++.dylib was compiled with
-fno-exceptions.

Unfortunately, fixing this is kind of tricky. The Standard has a few
req...

A bug with BlockIndent prevents line breaks within if (and else if)
clauses.

While fixing this bug, it appears that AlignAfterOpenBracket is not
designed to work with loop and if statements, but AlwaysBreak works on
if clauses. The documentation and tests are not clear on whether or not
this behavior is intended.

This PR preserves the `AlwaysBreak` behavior on `if` clauses without
supporting `BlockIndent` on `if` clauses to avoid regressions while
fixing the bug.

It may be reasonable to create an explicit option for alignment of if
(and loop) clauses intentionally for both `AlwaysBreak` and
`BlockIndent`

Fixes #54663.

Migrated from Differential Revision: https://reviews.llvm.org/D154755
See more discussion there. Addressed last open comment from the rev
about refactoring the complex conditional logic involved with the
`AlignAfterOpenBracket` line break behavior.

Following #77963, instructions like VMV_S_X/VMV_X_S 
handle single element, so the cost don't scale with LMUL.

Fixes #76991.

This PR implements `sys/getauxval`
that can be used in both overlay builds and full builds.

This matches the entrypoints for baremetal ARM.

Fat lto with -c compiles to an object file with the IR embedded in a
section of the object, the combination of fat-lto with -S should then
produce an assembly file equivalent of that. The IR output can still be
genreated by using both -S and -emit-llvm.

`R_ARM_PREL31` is a 31-bits relative data relocation where the
most-significant bit is preserved. It's used primarily in `.ARM.exidx`
sections, which we skipped processing until now, because we didn't
support the relocation type. This was implemented in RuntimeDyld with
https://reviews.llvm.org/D25069 and I implemented it in a similar way in
JITLink in order to reach feature parity.

This reverts commit 9a03d94a.

3ab8d2aa was reverted in bffd80d6.

[X86] Support encoding/decoding and lowering for APX variant SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD (#78853)

Four variants: promoted legacy, ND (new data destination), NF (no flags
update) and NF_ND (NF + ND).

The syntax of NF instructions is aligned with GNU binutils.
https://sourceware.org/pipermail/binutils/2023-September/129545.html

This reverts commit 3ab8d2aa.

This change is causing issues running lit tests on many bots including:
- https://lab.llvm.org/buildbot/#/builders/197/builds/12119
- https://lab.llvm.org/buildbot/#/builders/184/builds/9792
- https://lab.llvm.org/buildbot/#/builders/93/builds/18455
- https://lab.llvm.org/buildbot/#/builders/231/builds/19858
- https://lab.llvm.org/buildbot/#/builders/121/builds/38426
- https://lab.llvm.org/buildbot/#/builders/230/builds/23990
- https://lab.llvm.org/buildbot/#/builders/57/builds/32391
- https://lab.llvm.org/buildbot/#/builders/247/builds/13502
- https://lab.llvm.org/buildbot/#/builders/275/builds/3601
- https://lab.llvm.org/buildbot/#/builders/269/builds/4211
- https://lab.llvm.org/buildbot/#/builders/18/builds/14161
- https://lab.llvm.org/buildbot/#/builders/19/builds/23893
- https://lab.llvm.org/buildbot/#/builders/37/builds/30295
- https://lab.llvm.org/buildbot/#/builders/77/builds/33979

Fixes: 665f913e

Introduce two new categories:
- `_LIBCPP_ASSERT_VALID_DEALLOCATION`;
- `_LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL`.

This patch fixes linkage for platforms that don't implement
std::exception_ptr, as such setup was overlooked in #65534.

We want to emit stubs that match the instruction set state of the
relocation site. This is important for branches that have no built-in
switch for the instruction set state. It's the case for Jump24
relocations. Relocations on instructions that support switching on
the fly will be rewritten in a relaxation step in the future. This
affects Call relocations on `BL`/`BLX` instructions.

In this patch, the StubManager gains a second stub symbol slot for each
target and selects which one to use based on the relocation type. For
testing, we select the appropriate slot with a stub-kind filter, i.e.
`arm` or `thumb`. With that we can implement Armv7 stubs and test
that we can have both kinds of stubs for a single external symbol.

If offset is `addi rd, x0, imm`, merge imm into base offset.

VGPRs used for spilling do not require explicit reservation with MRI.
freezeReservedRegs() executed before register allocation ensures these
are placed in the reserve set.

The only pass after SILowerSGPRSpills is SIPreAllocateWWMRegs which
explicitly tests for interference before register allocation so should
not reuse a WWM VGPR holding spill data. reserveReg prevents calculation
of correct liveness for physical registers which could be used to extend
SIPreAllocateWWMRegs.