1. Apr 15, 2022
  2. Apr 14, 2022
    • Peter Klausler's avatar
      [flang] Fix combining cases of USE association & generic interfaces · 9b200074
      Peter Klausler authored
      Fortran admits a few ways to have multiple symbols with the
      same name in the same scope.  Two of them involve generic
      interfaces (from INTERFACE or GENERIC, the syntax doesn't matter);
      these are allowed to inhabit a scope with either a derived type or
      a subprogram that is also a specific procedure of the generic.
      (But not both a derived type and a subprogram; they could not
      cohabit a scope anyway, generic or not.)
      
      In cases of USE association, f18 needs to be capable of combining
      use-associated generic interfaces with other use-associated entities.
      Two generics get merged (this case was nearly correct); a generic
      and a derived type can merge into a GenericDetails with a shadowed
      derivedType(); and a generic can replace or ignore a use-associated
      procedure of the same name so long as that procedure is already
      one of its specifics.
      
      Further, these modifications to the use-associated generic
      interface must be made to a local copy of the symbol.  The previous
      code was messing directly with the symbol in the module's scope.
      
      The fix is basically a reimplementation of the member function
      DoAddUse() in name resolution.
      
      Differential Revision: https://reviews.llvm.org/D123704
      9b200074
    • John Brawn's avatar
      [AArch64] Add mayRaiseFPException to appropriate instructions · 27a8735a
      John Brawn authored
      This is mostly handled by adding "let mayRaiseFPException = 1" before
      the definition of the relevant instruction classes, but there are a
      couple of complications:
       * When we have a multiclass where currently some instantiations are
         of instructions that can raise an exception and others aren't we
         need to split that into two multiclasses, one inheriting from the
         other using a multiclass parameter to enable exceptions.
       * In a couple of places in the globalisel instruction selector we
         need to manually set the NoFPExcept flag. There's also another
         place that looks like it should need it, but that code is never hit
         for those opcodes due to them being handled by the generic
         instruction selector, so I've instead just removed them from the
         switch.
      
      Differential Revision: https://reviews.llvm.org/D115352
      27a8735a
    • John Brawn's avatar
      [AArch64] Adjust aarch64 constrained intrinsics tests and un-XFAIL · 1b1466c3
      John Brawn authored
      Remove the checking of the generated asm, as that's already tested
      elsewhere, and adjust some tests that were expecting the wrong
      intrinsic to be generated.
      
      Differential Revision: https://reviews.llvm.org/D118259
      1b1466c3
    • John Brawn's avatar
      [AArch64] Lowering and legalization of strict FP16 · 12c10226
      John Brawn authored
      For strict FP16 to work correctly needs some changes in lowering and
      legalization:
       * SelectionDAGLegalize::PromoteNode was missing handling for some
         strict fp opcodes.
       * Some of the custom lowering of strict fp operations needed to be
         adjusted to work with FP16.
       * Custom lowering needed to be added for round-to-int operations.
      
      With this, and the previous patches for the rest of the strict fp
      isel, we can set IsStrictFPEnabled = true.
      
      Differential Revision: https://reviews.llvm.org/D115620
      12c10226
    • Kevin P. Neal's avatar
      [FPEnv][InstSimplify] Fold fsub -0.0, -X ==> X · d43d9e1d
      Kevin P. Neal authored
      Currently the fsub optimizations in InstSimplify don't know how to fold
      -0.0 - (-X) to X when the constrained intrinsics are used. This adds partial
      support. The rest of the support will come later with work on the IR
      matchers.
      
      This review is split out from D107285.
      
      Differential Revision: https://reviews.llvm.org/D123396
      d43d9e1d
    • LLVM GN Syncbot's avatar
      [gn build] Port 1fdf952d · f80e4788
      LLVM GN Syncbot authored
      f80e4788
    • Chris Bieneman's avatar
      [HLSL] Add Semantic syntax, and SV_GroupIndex · 1fdf952d
      Chris Bieneman authored
      HLSL has a language feature called Semantics which get attached to
      declarations like attributes and are used in a variety of ways.
      
      One example of semantic use is here with the `SV_GroupIndex` semantic
      which, when applied to an input for a compute shader is pre-populated
      by the driver with a flattened thread index.
      
      Differential Revision: https://reviews.llvm.org/D122699
      
      # Conflicts:
      #	clang/include/clang/Basic/Attr.td
      #	clang/include/clang/Basic/AttrDocs.td
      1fdf952d
    • LLVM GN Syncbot's avatar
      [gn build] Port e471ba3d · 4f106515
      LLVM GN Syncbot authored
      4f106515
    • Joseph Huber's avatar
      [Object] Add binary format for bundling offloading metadata · e471ba3d
      Joseph Huber authored
      We need to embed certain metadata along with a binary image when we wish
      to perform a device-linking job on it. Currently this metadata was
      embedded in the section name of the data itself. This worked, but made
      adding new metadata very difficult and didn't work if the user did any
      sort of section linking.
      
      This patch introduces a custom binary format for bundling offloading
      metadata with a device object file. This binary format is fundamentally
      a simple string map table with some additional data and an embedded
      image. I decided to use a custom format rather than using an existing
      format (ELF, JSON, etc) because of the specialty use-case of this. We
      need a simple binary format that can be concatenated without requiring
      other external dependencies.
      
      This extension will make it easier to extend the linker wrapper's
      capabilties with whatever data is necessary. Eventually this will allow
      us to remove all the external arguments passed to the linker wrapper and
      embed it directly in the host's linker so device linking behaves exactly
      like host linking.
      
      Reviewed By: JonChesterfield
      
      Differential Revision: https://reviews.llvm.org/D122069
      e471ba3d
    • Joseph Huber's avatar
      [OpenMP] Make offloading sections have the SHF_EXCLUDE flag · 11f47b79
      Joseph Huber authored
      Offloading sections can be embedded in the host during codegen via a
      section. This section was originally marked as metadata to prevent it
      from being loaded, but these sections are completely unused at runtime
      so the linker should automatically drop them from the final executable
      or shard library. This flag adds support for the SHF_EXCLUDE flag in
      target lowering and uses it.
      
      Reviewed By: JonChesterfield, MaskRay
      
      Differential Revision: https://reviews.llvm.org/D122987
      11f47b79
    • Peter Klausler's avatar
      [flang] Improve appearance of message attachments · ef141aec
      Peter Klausler authored
      Error messages can have a list of attachments; these are used to point
      to related source locations, supply additional information, and to
      encapsulate error messages that were *not* emitted in a given context
      to explain why a warning was justified.
      
      This patch adds a message severity ("Because") for that last case,
      and extends to AttachTo() API to provide a means for overriding
      the severity of an attached message.
      
      Some existing message attachments had their severities adjusted,
      now that we're printing them.  And operator==() for Message was
      cleaned up while debugging after I noticed that it was recursively
      O(N**2) and subject to returning a false positive.
      
      Differential Revision: https://reviews.llvm.org/D123710
      ef141aec
    • Fabian Wolff's avatar
    • David Green's avatar
      [AArch64] Move v4i8 concat load lowering to a combine. · 1ba8f4f6
      David Green authored
      The existing code was not updating the uses of loads that it recreated,
      leading to incorrect chains which could break the ordering between
      nodes. This moves the code to a combine instead, and makes sure we
      update the chain references. This does mean it happens earlier -
      potentially before the concats are simplified. This can lead to
      inefficiencies in the codegen, which will be fixed in followups.
      1ba8f4f6
    • Andrew Savonichev's avatar
      [NVPTX] Fix barrier.ll LIT test · b6183a57
      Andrew Savonichev authored
      The second parameter should be a multiple of the warp size (32).
      
      PTX ISA spec, s9.7.12.1. Parallel Synchronization and Communication
      Instructions: bar, barrier
      
      barrier.sync{.aligned}      a{, b};
      
      Operand b specifies the number of threads participating in the
      barrier. If no thread count is specified, all threads in the CTA
      participate in the barrier. When specifying a thread count, the value
      must be a multiple of the warp size.
      
      Differential Revision: https://reviews.llvm.org/D123470
      b6183a57
    • Andrew Savonichev's avatar
      [NVPTX] Avoid dots in global names · 32949401
      Andrew Savonichev authored
      It seems that ptxas cannot parse them:
      ptxas fatal: Parsing error near '.2': syntax error
      
      Differential Revision: https://reviews.llvm.org/D123041
      32949401
    • Andrew Savonichev's avatar
      [NVPTX] .attribute(.managed) is only supported for sm_30 and PTX 4.0 · 4cef5c39
      Andrew Savonichev authored
      PTX ISA spec, s5.4.8. Variable Attribute Directive: .attribute
      
      PTX ISA Notes
      Introduced in PTX ISA version 4.0.
      
      Target ISA Notes
      .managed attribute requires sm_30 or higher.
      
      Differential Revision: https://reviews.llvm.org/D123040
      4cef5c39
    • Andrew Savonichev's avatar
      [NVPTX] shfl.sync is introduced in PTX 6.0 · 230f3269
      Andrew Savonichev authored
      PTX ISA spec, s9.7.8.6. Data Movement and Conversion Instructions:
      shfl.sync
      
      PTX ISA Notes
      Introduced in PTX ISA version 6.0.
      
      Target ISA Notes
      Requires sm_30 or higher.
      
      Differential Revision: https://reviews.llvm.org/D123039
      230f3269
    • Andrew Savonichev's avatar
      [NVPTX] 64-bit atom.{and,or,xor,min,max} require sm_32 or higher · 369adba0
      Andrew Savonichev authored
      PTX ISA spec, s9.7.12.4. Parallel Synchronization and Communication
      Instructions: atom
      
      Target ISA Notes
      64-bit atom.{and,or,xor,min,max} require sm_32 or higher.
      
      Differential Revision: https://reviews.llvm.org/D123038
      369adba0
    • LLVM GN Syncbot's avatar
      [gn build] Port 58d9ab70 · 5bf9aa38
      LLVM GN Syncbot authored
      5bf9aa38
    • Nikolas Klauser's avatar
      [libc++][ranges] Implement ranges::minmax and ranges::minmax_element · 58d9ab70
      Nikolas Klauser authored
      Reviewed By: var-const, #libc, ldionne
      
      Spies: sstefan1, ldionne, BRevzin, libcxx-commits, mgorny
      
      Differential Revision: https://reviews.llvm.org/D120637
      58d9ab70
    • PeixinQiao's avatar
      [flang] Fix intrinsic interface for DIMAG/DCONJG · 0b55a8dc
      PeixinQiao authored
      The intrinsics DREAL, DIMAG, and DCONJG are from Fortran 77 extensions.
      For DREAL, the type of argument is extended to any complex. For DIMAG
      and DCONJG, the type of argument for them should be complex(8). For DIMAG,
      the result type should be real(8). For DCONJG, the result type should be
      complex(8). Fix the intrinsic interface for them and add test cases for
      the semantic checks and the lowering.
      
      Reviewed By: Jean Perier
      
      Differential Revision: https://reviews.llvm.org/D123459
      0b55a8dc
    • PeixinQiao's avatar
      [flang] Fix float-number representation bug · 0ff32224
      PeixinQiao authored
      The float number is represented as (-1)^s * 1.f * 2^(-127) for 32-bit,
      where s is the signed flag, f is the mantissa. When the exponent bits
      are all zeros, the float number is represented as (-1)^s * 0.f *2^(-126)
      for 32-bit, in which case, the intPart is '0'.
      
      Reviewed By: Jean Perier
      
      https://reviews.llvm.org/D123673
      0ff32224
    • Alex Zinenko's avatar
      [mlir] fix compiler warnings · e5a5e008
      Alex Zinenko authored
      -Wsign-compare and -Wunsued-value in the recently introduced code.
      e5a5e008
    • LLVM GN Syncbot's avatar
      [gn build] Port dd47ab75 · 65fcd31e
      LLVM GN Syncbot authored
      65fcd31e
    • Nico Weber's avatar
      Revert "[clang-tidy] Add portability-std-allocator-const check" · dd47ab75
      Nico Weber authored
      This reverts commit 73da7eed.
      Breaks check-clang-tools on Windows, see comment on
      https://reviews.llvm.org/D123655
      dd47ab75