It's called BaseSize in the Record class as well, so call it BaseSize
when creating the Record.

Handle DeclRefExprs of enum types. They are otherwise handled like
integers.

Differential Revision: https://reviews.llvm.org/D134020

The type information is lost when pushing things on the stack. When
later pop()ing items of the wrong type, we can instead simply get
garbage values and those problems are hard to find. Add another stack to
record the type of item we pushed and use that for debugging.

Differential Revision: https://reviews.llvm.org/D133941

Implement visiting UnaryExprOrTypeTraitExprs to handle sizeof()
expressions.

Differential Revision: https://reviews.llvm.org/D133934

Instead of two overloads, use a if constexpr to differentiate between
pointer and non-pointer parameters

We don't need the full include here.

This is dead code right now but will be used for implementing array
fillers, where we need some information from the initializer when
allocaing the Descriptors.

Differential Revision: https://reviews.llvm.org/D133856

Reviewed By: spupyrev

Differential Revision: https://reviews.llvm.org/D134819

In D132837, an existing v_fma combine was extended to regard nested
fma instructions. Originally, the inner FMA was checked for being used
only once. In its current state, this check is missing, which causes
some regressions.

In this patch, this check was added.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D134856

Factor out the logic to create induction resume values for a specific
induction. This will be used in D92132 to support widened IVs during
epilogue vectorization.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D134211

This cc1 option -fallow-half-arguments-and-returns allows __fp16 to be
passed by argument and returned, without giving an error. It is
currently always enabled for Arm and AArch64, by forcing the option in
the driver. This means any cc1 tests (especially those needing
arm_neon.h) need to specify the option too, to prevent the error from
being emitted.

This changes it to a target option instead, set to true for Arm and
AArch64. This allows the option to be removed. Previously it was implied
by -fnative_half_arguments_and_returns, which is set for certain
languages like open_cl, renderscript and hlsl, so that option now too
controls the errors. There were are few other non-arm uses of
-fallow-half-arguments-and-returns but I believe they were unnecessary.
The strictfp_builtins.c tests were converted from __fp16 to _Float16 to
avoid the issues.

Differential Revision: https://reviews.llvm.org/D133885

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D134808

This patch disables MC/ELF/cfi-version.ll test as windows does not emit
.debug_frame needed by the test. This was previously disabled for arm64
but windows on arm uses aarch64-pc-windows* triple. Replacing arm64 with
aarch64 to accomodate windows aarch64 triple(s).

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D134863

Reviewed By: pifon2a

Differential Revision: https://reviews.llvm.org/D134834

[WinEH] Prepare test win64-funclet-preisel-intrinsics.ll for extension to nested try-catch case (NFC)

[mlir][memref]Add pattern to forward memref.extract_aligned_pointer_as_index(view_like_op) to its source

Differential Revision: https://reviews.llvm.org/D134835

[DebugInfo][InferAddressSpaces] Propagate DebugLoc when cloning an instruction in InferAddressSpaces

Differential Revision: https://reviews.llvm.org/D134428

In addition, replace outdated XFAIL test by a new one.

Differential Revision: https://reviews.llvm.org/D134439

Simplify the code by using CastInst::CreateBitOrPointerCast directly. By
not going through the builder, the temporary instruction also won't get
registered in InsertedValues & co, which means less work overall and
simplifies the clean-up.

Although the instruction names begin "frint", the ACLE spec states that
the intrinsic names begin "__rint", without the "f".

Differential Revision: https://reviews.llvm.org/D134824

This turned out to be insufficient by itself, because we would
also need to export config.guess.

This reverts commit 4ac4d6bc.

This reverts commit b7baddc7.

Broke CodeGen/X86/callbr-asm-kill.mir
We shall pay attention when adding new constraints.

And default auxIdx to 0.

Driver options usually use `Joined` instead of `Separate`. It is also weird that
`--config-system-dir=`/etc exist while `--config=` did not exist.

Reviewed By: mgorny

Differential Revision: https://reviews.llvm.org/D134790

This is formally invalid, and causes build errors when building with
clang in -std=c++20.

http://eel.is/c%2B%2Bdraft/vector.overview#4

- Use `fneg %a` instead of `fsub -0.0, %a`
  - This is for D134354 as we don't currently support folding `fsub -0.0, %a` into `fneg` on GISel.
    Also, `fneg` is the canonical way to do the negation.
- Switch to `update_llc_test_checks`-generated tests.
  - Better test coverage
  - Easier to update
  - Easier to see changes in future diffs
- Remove unnecessary CL arguments in RUN lines

Motive for the patch: Preparation for D134354 - we would like to
put GISel tests in this file as well. Fixing the lack of `fneg` and
switching to generated testing makes it much easier.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D134793

k: A memory operand whose address is formed by a base register and
(optionally scaled) index register.

m: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as st.w and ld.w.

ZB: An address that is held in a general-purpose register. The offset
is zero.

ZC: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as ll.w and sc.w.

Differential Revision: https://reviews.llvm.org/D134638

Trigger some "libatomic" error.

This reverts commit ccbb4014.

This is only invoked from a single site and doesn't add any value.

This patch removes the dependency to the legacy pass manager when
building llvm-stress.

Instead of setting up a pass manager at all we just run verifyModule()
to check that the generated IR satisfies the verifier, and then
we use Module::print() to output the IR. No need to setup passes and
populating a pass manager since we aren't doing anything more fancy
than that.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D134802

(Probably) fixes https://crbug.com/1355639

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D134825

This change sets
-amdgpu-assume-{external-call-stack-size | dynamic-stack-object-size}
options to zero by default for code object v5 and later. The runtime is
expected to adjust the scratch size if the amdhsa_uses_dynamic_stack bit
in the kernel descriptor is set.

Differential Revision: https://reviews.llvm.org/D128346

On a debug build with _LIBCPP_DEBUG_RANDOMIZE_UNSPECIFIED_STABILITY
enabled from 100 executions around 80 are failing.

More details in https://reviews.llvm.org/D125776#3820399

The issue is related to the use of std::sort.

Reviewed By: antondaubert, jryans, probinson

Differential Revision: https://reviews.llvm.org/D134805

This is very useful when you want to parse IR even if
its invalid (e.g. bytecode). It's also useful if you don't
want to pay the cost of verification in certain situations.

Differential Revision: https://reviews.llvm.org/D134847