This should have been part of D154585.

Make the transformation accessible to other drivers (i.e., passes).

Fold allsignbits pack patterns to make better use of cheap (and commutable) logic ops

Reapplied after a32d14fd / 156913cb with bitcast fix

The TileOp builders did not set `scalable_sizes`, which produces invalid ops. `scalable_sizes` must contain as any booleans as there are sizes.

Differential Revision: https://reviews.llvm.org/D154585

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D153340

Fixes a bug that prevents alignment from proceeding through a function
pointer in a list of declarations.

Fixes #63451.

Differential Revision: https://reviews.llvm.org/D153585

Fixes a bug with the handling of right aligned references with left/middle
alignment pointers.

Fixes #63452.

Differential Revision: https://reviews.llvm.org/D153579

Previously the following would crash:
(lldb) run
Process 2594053 launched: '/tmp/test.o' (aarch64)
Process 2594053 exited with status = 0 (0x00000000)
(lldb) register read <tab>

As the completer assumed that the execution context would always
have a register context. After a program has finished, it does not.

Split out the generic parts of the test from the x86 specific tests,
and added "register info" to both.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D154413

This matches the data type of the intrinsics. This case be seen
from the removal of sext and trunc instructions from the IR.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D154572

These builtins were recently changed to return 'int' like the
similar __builtin_clz/__builtin_ctz builtins, but the IR generation
was not updated to use a truncate.

`JITLinkContext` is notified (using `notifyResolved`) of the final
symbol addresses after allocating memory and running the post-allocation
passes. However, linker relaxation, which can cause symbol addresses to
change, was run during the pre-fixup passes. This causes users of
JITLink (e.g., ORC) to pick-up wrong symbol addresses when linker
relaxation was enabled.

This patch fixes this by running relaxation during the post-allocation
passes.

Fixes #63671

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D154501

This patch adds the missing logic to vectorise `tensor.extract` for 0-d
tensors.

Fixes #63688

Differential Revision: https://reviews.llvm.org/D154518

This matches the definition for the underlying builtins and what
is done in the Zbb test.

Summary: Clang uses LLVM's integrated assembler by default on most targets, however non-integrated-as mode is default on AIX. Currently integrated-as mode on AIX has passed tests of LLVM test-suite, bootstrap and Spec2017, therefore this patch sets integrated-as as the default assembler mode on AIX.

Reviewed By: DiggerLin

Differential Revision: https://reviews.llvm.org/D150758

As reported at https://reviews.llvm.org/D153305#4475840.

The issue: https://github.com/llvm/llvm-project/issues/63704

[InstCombine] Transform (A > 0) | (A < 0) -> zext (A != 0) fold

This extends **foldCastedBitwiseLogic** to handle the similar cases.

Actually, for `(A > B) | (A < B)`, when B != 0, it can be optimized to `zext( A != B )` by **foldAndOrOfICmpsUsingRanges**.
However, when B = 0, **transformZExtICmp** will transform `zext(A < 0) to i32` into `A << 31`,
which cannot be optimized by **foldAndOrOfICmpsUsingRanges**.

Because I'm new to LLVM and has no concise knowledge about how LLVM decides the order of optimization,
I choose to extend **foldCastedBitwiseLogic** to fold `( A << (X - 1) ) | ((A > 0) zext to iX) -> (A != 0) zext to iX`.

And the equivalent fold follows:
```
 A << (X - 1) ) | ((A > 0) zext to iX
  -> A < 0 | A > 0
  -> (A != 0) zext to iX
```

It's proved by [[https://alive2.llvm.org/ce/z/33HzjE|alive-tv]]

Related issue:
[[https://github.com/llvm/llvm-project/issues/62586  | (a > b) | (a < b) is not simplified only for the case b=0 ]]

Reviewed By: goldstein.w.n

Differential Revision: https://reviews.llvm.org/D154126

Tests for an upcoming  (A > 0) | (A < 0) -> zext (A != 0) fold.
Related issue:
[[ https://github.com/llvm/llvm-project/issues/62586 | (a > b) | (a < b) is not simplified only for the case b=0 ]]

Differential Revision: https://reviews.llvm.org/D154089

See comments in the code for details.

Reviewed By: xazax.hun

Differential Revision: https://reviews.llvm.org/D154479

1. Improved code that deduces register class from instruction definitions. Previously if some instruction didn't contain a reg class for an operand it was considered as no information on register class even if other instructions specified the class.

2. Added check on required size of resulting register because in some cases classes with smaller registers had been selected (for example VReg_1).

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D152832

[LibCallsShrinkWrap] Set IsFPConstrained is true for creating quiet floating comparision if function has strictfp attribute

Create a quiet floating-point comparision if function has strictfp attribute.
Avoid unexpected FP exception raised during libcall domain error checking.
It raises an FP exception only in case where an input is a signaling NaN.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D152776

fdr-thread-order.cpp can be very slow when the thread contention is large.
Enable it for AArch64 and x86-64 for now.

fdr-mode.cpp fails on a ppc64le machine. Unsupport it on ppc64le for now.

The remaining modified tests pass on AArch64, ppc64le, and x86-64.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154487

A project that bundles the llvm source code may have their own
PACKAGE_VERSION variable, so only use this to compute the
CLANG_RESOURCE_DIR if CLANG_VERSION_MAJOR is undefined.

Reviewed By: sebastian-ne

Differential Revision: https://reviews.llvm.org/D152608

Mark loongarch64 as supported for profile. All tests passed.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D154405

These are redundant.  The same dependencies are being added as part
of the add_llvm_component_library() call.  I confirmed this by diff'ing
the build.ninja files before and after the change and saw no change.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153166

Follow up of D143999 and follow
https://mlir.llvm.org/getting_started/DeveloperGuide/#ir-verifier.

Fixes #60808.

This pattern started showing up more after D151284

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154435

Differential Revision: https://reviews.llvm.org/D154541

Fixes #63661

https://reviews.llvm.org/D154555

[ODRHash] Stop hashing `ObjCMethodDecl::isPropertyAccessor` as it doesn't capture inherent method quality.

`isPropertyAccessor` depends on the surrounding code and not on the method
itself. That's why it can be different in different modules. And
mismatches shouldn't be an error.

rdar://109481753

Differential Revision: https://reviews.llvm.org/D154460

[ODRHash] Stop hashing `ObjCMethodDecl::isOverriding` as it doesn't capture inherent method quality.

`isOverriding` depends on the surrounding code and not on the method
itself. That's why it can be different in different modules. And
mismatches shouldn't be an error.

rdar://109481753

Differential Revision: https://reviews.llvm.org/D154459

We don't expect this to be used on RV32 currently so remove it
to reduce number of entries in the isel table.

Teach RegisterInfoEmitter.cpp to allow a type to be missing for
a particular HwMode.